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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our current design operated on lowest sampling speed. Length matching becomes critical in future version with higher sampling rates, then cable length must be matched. However SATA cabling technology is prepared for that case and matched SATA cables are standard merchandise.
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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our current design operated on lowest sampling speed. Length matching becomes critical in future version with higher sampling rates, then cable length must be matched. However SATA cabling technology is prepared for that case and matched SATA cables are standard merchandise.
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\secc ADC modules design
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\secc ADC modules design
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\midinsert
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\picw=10cm \cinspic ./img/ADCdual_Top.png
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\picw=10cm \cinspic ./img/ADCdual_Bottom.png
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\caption/f FPGA ML605 development board.
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\endinsert
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\secc ADC selection
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\secc ADC selection
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There exist several ADC signaling formats currently used in communication with FPGA.
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There exist several ADC signaling formats currently used in communication with FPGA.
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Complete schematic diagram of ADCdual01A module board is included in the appendix.
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Complete schematic diagram of ADCdual01A module board is included in the appendix.
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\secc ADC modules interface
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\secc ADC modules interface
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\midinsert
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\picw=10cm \cinspic ./img/FMC2DIFF_top.png
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\picw=10cm \cinspic ./img/FMC2DIFF_Bottom.png
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\caption/f FPGA ML605 development board.
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\endinsert
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Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
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Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
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This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
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This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
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The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
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The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
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Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
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Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
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Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface].
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Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface].
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\midinsert \clabel[xillybus-interface]{Grabber binary output format}
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\midinsert \clabel[xillybus-interface]{Grabber binary output format}
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\ctable {clllllllll}{
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\ctable {clllllllll}{
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\hfil
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- |
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& \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
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\hfil & \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
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Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr
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Data name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \cr
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Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
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Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
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Content & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr
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Content & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr
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}
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}
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\caption/t System device "/dev/xillybus_data2_r" data format
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\caption/t System device "/dev/xillybus_data2_r" data format
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\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
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\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
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\caption/f Meteor reflection received by evaluation setup.
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\caption/f Meteor reflection received by evaluation setup.
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\endinsert
|
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\endinsert
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\midinsert
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\midinsert
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\clabel[phase-phase-difference]{Phase difference}
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\clabel[phase-difference]{Phase difference}
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\picw=10cm \cinspic ./img/screenshots/phase_difference.png
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\picw=10cm \cinspic ./img/screenshots/phase_difference.png
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\caption/f Demonstration of phase difference between antennas.
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\caption/f Demonstration of phase difference between antennas.
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\endinsert
|
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\endinsert
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|
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For simplest demonstration of phase difference between antennas, we analyse part of signal by complex conjugate multiplication between channels. Result of this analysis can be seen on picture \ref[phase-difference]. Points of selected part of signal creates clear vector, which illustrates the presence of phase difference.
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We use ACOUNT02A device for frequency checking on both local oscillators.
|
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We use ACOUNT02A device for frequency checking on both local oscillators.
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%\sec Simple passive Doppler radar
|
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%\sec Simple passive Doppler radar
|
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408 |
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