Subversion Repositories svnkaklik

Rev

Rev 1125 | Rev 1132 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log

Rev 1125 Rev 1130
Line 4... Line 4...
4
 
4
 
5
The final design will eventually become a part of MLAB Advanced Radio Astronomy System. 
5
The final design will eventually become a part of MLAB Advanced Radio Astronomy System. 
6
 
6
 
7
\sec Possible hardware improvements
7
\sec Possible hardware improvements
8
 
8
 
9
PCB design of used modules might need more precise high speed optimization of differential pairs. Improvement in high-speed routing allows possible use of fastest ADC from  Linear Technology devices family.  Use of faster ADCs even improve range of possible usage. 
9
The PCB design of the used modules might need more precise high-speed optimalization of differential pairs. Improvement in high-speed routing allows a possible use of the fastest ADC from the Linear Technology devices family. The use of the faster ADCs even improve a range of possible usages. 
10
 
10
 
11
 
11
 
12
\secc ADC modules weakness
12
\secc ADC modules weakness
13
 
13
 
14
Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest. 
14
Several ADC module imperfections, such as the unnecessary separation of FRAME and DCO signal to two connectors, should be mitigated. These two signals should be merged together to one SATA connector. With this modification we are able to remove one redundant SATA cable between the analog to digital converter nest and between computational unit nest. 
15
 
15
 
16
\sec Possible software improvements
16
\sec Possible software improvements
17
 
17
 
18
In future versions of device, the Xillybus IP core and interface should be swapped with an open-source alternative PCIe interfacing module or PCIe may be completely avoided.   
18
In the future versions of the device, the Xillybus IP core and interface should be swapped with an open-source alternative PCIe interfacing module or PCIe might be completely avoided.   
19
 
19
 
20
 
20
 
21
SPI configuration data read back should be implemented. 
21
SPI configuration data read back should be implemented. 
22
 
22
 
23
\bibchap
23
\bibchap