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\chap Conclusion 

\chap Conclusions

A special design of scalable data-acquisition system was proposed. This system has unique parameters compared to the state of the art radioastronomy signal processing hardware. Offering a 16bit resolution and comparable dynamical range is more than other similar constructions could offer.  We demonstrated system functionality on the most basic interferometric station. Further validation of reached parameters would be necessary. Following that, the final design will eventually become a part of MLAB Advanced Radio Astronomy System\cite[mlab-aras]. 

A special design of the scalable data-acquisition system was proposed. This system has unique parameters compared to the state of the art radioastronomy signal processing hardware. The outcome of this diploma project offers the 16bit resolution and such a dynamical range which is not common with others. The conducted experiments demonstrated the system functionality in the instance of the most basic interferometric station. Additional validation of reached parameters would be necessary, though. The fully functional trial version of the fast multi-channel data acquisition part of the radioastronomy receiver was designed and tested in the reported diploma project.

All requirements demanded by the thesis specification have been reached or exceed. The required minimal sampling frequency of 1 MHz has been exceeded five times at least. Requested dynamical range specified by 12 bit have been exceeded at least by 8 dB in the decibel scale. As a by-pass product of digitalisation unit design the software defined GPS disciplined oscillator device has been developed. This device is currently in use on several radio meteor detection stations in Czech Republic.

All requirements demanded by the thesis specification have been reached and/or exceeded. The required minimal sampling frequency of 1 MHz has been exceeded five times at least. The requested dynamical range specified by 12 bits have been exceeded at least by 8 dB in the decibel scale. As a by-pass product of digitization unit design, the software defined GPS disciplined oscillator device has been developed. This device is currently in use in several radio meteor detection stations in the Czech Republic. On other hand the proposed design is not still perfect and some minor imperfections should be corrected in future work.

On other hand the proposed design is not still perfect and some minor imperfections should be corrected in the future work. 

The work also attracted the interest of the research team at the Czech Technical University in Prague, Faculty of Electrical Engineering in the project MUMOIRE, which has been solved in collaboration and for the US Missile Defense Agency. MUMOIRE team seeks space debris detection/observation methods, which fuse observations from the optical telescope and the radar. The multi-channel data acquisition part of the receiver should provide better radar observations in which French radar GRAVES serves as the energy source.

The PCB design of the used modules might need more precise high-speed optimization of differential pairs. Improvement in high-speed routing allows a possible use of the fastest ADC from the Linear Technology devices family. The use of faster ADCs even improves a range of possible usages.  Minor ADC module imperfections, such as the unnecessary separation of FRAME and DCO signal to two connectors, should be mitigated. These two signals should be merged together to one SATA connector. With this modification we will be able to remove one redundant SATA cable between the analog to digital converter device and computational unit section. 

Minor ADC module imperfections, such as the unnecessary separation of FRAME and DCO signal to two connectors, should be mitigated. These two signals should be merged together to one SATA connector. With this modification, we will be able to remove one redundant SATA cable between the analog to digital converter device and the computational unit section.

In the future versions of the system hardware, the Xillybus IP core and driver interface should be swapped with an open-source alternative of PCIe interfacing module or PCIe might be completely avoided. In ADC configuration FPGA module, the SPI configuration data registers read back should be implemented. 

In the future versions of the system hardware, the Xillybus IP core and driver interface should be swapped with an open-source alternative of PCIe interfacing module or PCIe might be completely avoided. In ADC configuration FPGA module, the SPI configuration data registers read back should be implemented.

\nonum \chap Glossary 

\nonum \chap Glossary