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\chap Conclusion
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\chap Conclusion
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Special design of scalable data-acquisition system was proposed. This system has unique parameters compared to state of the art radioastronomy signal processing hardware. Offered 16bit resolution and related dynamical range is more than other similar constructions could offer. We demonstrated system working on the most basic interferometric station. Other validation of reached parameters should be needed. After that, the final design will eventually become a part of MLAB Advanced Radio Astronomy System\cite[mlab-aras].
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A special design of scalable data-acquisition system was proposed. This system has unique parameters compared to the state of the art radioastronomy signal processing hardware. Offering a 16bit resolution and comparable dynamical range is more than other similar constructions could offer. We demonstrated system functionality on the most basic interferometric station. Further validation of reached parameters would be necessary. Following that, the final design will eventually become a part of MLAB Advanced Radio Astronomy System\cite[mlab-aras].
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All requirements demanding by specification have been reached or exceed. The required minimal sampling frequency 1 MHz has been exceeded fifth times at least. Requested dynamical range specified by 12 bit have been exceeded at least by 8 dB in decibel scale. As by-pass product of digitalisation unit design the software defined GPS disciplined oscillator device has been developed. This device is currently in use in several radio meteor detection station in Czech Republic.
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All requirements demanded by the thesis specification have been reached or exceed. The required minimal sampling frequency of 1 MHz has been exceeded five times at least. Requested dynamical range specified by 12 bit have been exceeded at least by 8 dB in decibel scale. As by-pass product of digitalisation unit design the software defined GPS disciplined oscillator device has been developed. This device is currently in use on several radio meteor detection stations in Czech Republic.
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On other hand the proposed design is not still perfect and some minor imperfections should be corrected in future work.
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On other hand the proposed design is not still perfect and some minor imperfections should be corrected in future work.
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\sec Possible hardware improvements
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\sec Possible hardware improvements
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The PCB design of the used modules might need more precise high-speed optimization of differential pairs. Improvement in high-speed routing allows a possible use of the fastest ADC from the Linear Technology devices family. The use of the faster ADCs even improve a range of possible usages. Minor ADC module imperfections, such as the unnecessary separation of FRAME and DCO signal to two connectors, should be mitigated. These two signals should be merged together to one SATA connector. With this modification we are able to remove one redundant SATA cable between the analog to digital converter device and between computational unit section.
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The PCB design of the used modules might need more precise high-speed optimization of differential pairs. Improvement in high-speed routing allows a possible use of the fastest ADC from the Linear Technology devices family. The use of the faster ADCs even improves a range of possible usages. Minor ADC module imperfections, such as the unnecessary separation of FRAME and DCO signal to two connectors, should be mitigated. These two signals should be merged together to one SATA connector. With this modification we will be able to remove one redundant SATA cable between the analog to digital converter device and computational unit section.
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\sec Possible software improvements
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\sec Possible software improvements
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In the future versions of the system hardware, the Xillybus IP core and driver interface should be swapped with an open-source alternative of PCIe interfacing module or PCIe might be completely avoided. In ADC configuration FPGA module, the SPI configuration data registers read back should be implemented.
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In the future versions of the system hardware, the Xillybus IP core and driver interface should be swapped with an open-source alternative of PCIe interfacing module or PCIe might be completely avoided. In ADC configuration FPGA module, the SPI configuration data registers read back should be implemented.
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