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Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market. Combination of the required parameters -- dynamic range which needs at least 16bit and a minimum sampling frequency of 1 MSPS, leads to high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.
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20 |
Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market. Combination of the required parameters -- dynamic range which needs at least 16bit and a minimum sampling frequency of 1 MSPS, leads to high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.
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\sec System scalability
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\sec System scalability
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For analog channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ACD module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. Then the digital signal can be conducted even through long wires.
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For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ADC module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. Then the digital signal can be conducted even through long wires.
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.)
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.)
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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28 |
This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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In this section testing system will be described.
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In this section testing system will be described.
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\secc Frequency synthesis
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\secc Frequency synthesis
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We have used centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used while other working frequencies have been derived by its division. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by specification.}
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We have used centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used while other working frequencies have been derived by its division. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by specification.}
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This method has been used in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.
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Frequency monitoring compensation method has been used in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- SATA cable should be used for this purpose.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock delivered by FPGA from main local oscillator. This signal should use high quality differential signalling cable -- SATA cable should be used for this purpose.
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\secc Signal cable connectors
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\secc Signal cable connectors
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Several widely used and commercially easily accessible differential connectors were considered.
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Several widely used and commercially easily accessible differential connectors were considered.
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\secc Design of ADC modules
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\secc Design of ADC modules
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This modules have MLAB standard construction with four mounting holes in corner aligned in defined raster.
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This modules have MLAB standard construction with four mounting holes in corner aligned in defined raster.
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Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel. This signal concept enables selection of proper bus bitwidth according to sampling rate. (Higher bus bit-width downgrades signalling speed and vice versa.)
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Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel. This signal concept enables selection of proper bus bit-width according to sampling rate. (Higher bus bit-width downgrades signalling speed and vice versa.)
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For connection of this signaling layout, miniSAS to multiple SATA cable should be used.
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For connection of this signalling layout, miniSAS to multiple SATA cable should be used.
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For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad. And much better than widely used Eagle software.
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For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad. And much better than widely used Eagle software.
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New PCB footprints have been designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. And they are now publicly accessible from official KiCAD repository at GitHub.
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New PCB footprints have been designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. And they are now publicly accessible from official KiCAD repository at GitHub.
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\secc ADC selection
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\secc ADC selection
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| 95 |
Several ADC signaling formats currently exist for communication with FPGA.
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Several ADC signalling formats currently exist for communication with FPGA.
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\begitems
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\begitems
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| 98 |
* DDR LVDS
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* DDR LVDS
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| 99 |
* JEDEC 204B
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* JEDEC 204B
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| 100 |
* JESD204A
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* JESD204A
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All parts in this category are compatible with one board layout. Main differences are in sampling frequency and signal to noise ratio. The slowest one has maximal sampling frequency 20 MHz. But all types have minimal sampling frequency 5 MSPS. All types were configurable over serial interface (SPI). SPI seems to be a standard for high-end ADC chips from main manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
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All parts in this category are compatible with one board layout. Main differences are in sampling frequency and signal to noise ratio. The slowest one has maximal sampling frequency 20 MHz. But all types have minimal sampling frequency 5 MSPS. All types were configurable over serial interface (SPI). SPI seems to be a standard for high-end ADC chips from main manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
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\secc ADC modules interface
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\secc ADC modules interface
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All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3.
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All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3.
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This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix.
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This specification guarantee compatibility with others FPGA board which has FMC LPC connector for Mezzanine Card. Schematic diagram of this adapter board is included in appendix.
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Primary purpose of this PCB is to enable connection of ADC modules from space excluded from PC case. (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques).
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Primary purpose of this PCB is to enable connection of ADC modules from space excluded from PC case. (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques).
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Differential signaling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality.
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Differential signaling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality.
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\midinsert
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\midinsert
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\midinsert
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
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\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
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| 187 |
\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.
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\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.
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\endinsert
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\endinsert
|
| 189 |
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| 190 |
T
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| 191 |
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|
| 192 |
ADC1 CH1 maximal input 705.7 mV
|
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ADC1 CH1 maximal input 705.7 mV
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\midinsert
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\midinsert
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But this systems and cables are still very expensive. For example (http://www.opalkelly.com/products/xem6110/) has price tag 995 USD at time of writing this thesis.
|
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But this systems and cables are still very expensive. For example (http://www.opalkelly.com/products/xem6110/) has price tag 995 USD at time of writing this thesis.
|
| 224 |
Therefore better approach must be found.
|
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Therefore better approach must be found.
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\sec Parralella board computer
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\sec Parralella board computer
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Parallella is gon
|
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%Parallella is gon
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\sec GPU based computational system
|
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\sec GPU based computational system
|
| 231 |
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|
| 232 |
A new GPU development board NVIDIA K1 has been released in recent time it is shown on image \ref[img-NVIDIA-K1]. This board are intended for use in computer vision, robotics, medicine, security, and automotive. This board has ideal parameters for signal processing for this relatively low price 192 USD. But it is currently in pre-order release stage (in April 2014).
|
231 |
A new GPU development board NVIDIA K1 has been released in recent time it is shown on image \ref[img-NVIDIA-K1]. This board are intended for use in computer vision, robotics, medicine, security, and automotive. This board has ideal parameters for signal processing for this relatively low price 192 USD. But it is currently in pre-order release stage (in April 2014).
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| Line 235... |
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| 235 |
\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
|
234 |
\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
|
| 236 |
\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
|
235 |
\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
|
| 237 |
\caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}.
|
236 |
\caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}.
|
| 238 |
\endinsert
|
237 |
\endinsert
|
| 239 |
|
238 |
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| 240 |
|
- |
|
| 241 |
|
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|
| 242 |
\chap Conclusion
|
- |
|
| 243 |
|
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|
| 244 |
Special design of scalable data-aquisition system was proposed. This system has parameters
|
- |
|
| 245 |
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|
| 246 |
\sec Possible future improvements
|
- |
|
| 247 |
|
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|
| 248 |
Several ADC module imperfections, such as useless separation of FRAME and DCO signal to two connectors, should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest.
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- |
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