Subversion Repositories svnkaklik

Rev

Rev 1119 | Rev 1122 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log

Rev 1119 Rev 1121
Line 213... Line 213...
213 
Signal configuration used in our trial design is described in the following tables.
213 
Signal configuration used in our trial design is described in the following tables.
214 
 
 214 
 
215 
%% zapojeni SPI, FPGA zpatky necte konfiguraci, ale je tam na slepo nahravana.
 215 
%% zapojeni SPI, FPGA zpatky necte konfiguraci, ale je tam na slepo nahravana.
216 
 
 216 
 
217 
 
 217 
 
- 
 
 218 
 
- 
 
 219 
\midinsert \clabel[minisas-interface]{Grabber binary output format}
- 
 
 220 
\ctable {cccc}
- 
 
 221 
{
- 
 
 222 
miniSAS	&	SATA pair	&	FMC signal	&	Used as	\cr
- 
 
 223 
P0	&	1	&	LA03	&	 not used 	\cr
- 
 
 224 
P0	&	2	&	LA04	&	 not used 	\cr
- 
 
 225 
P1	&	1	&	LA08	&	 not used 	\cr
- 
 
 226 
P1	&	2	&	LA07	&	 not used 	\cr
- 
 
 227 
P2	&	1	&	LA16	&	ADC1  CH1 (LTC2190)	\cr
- 
 
 228 
P2	&	2	&	LA11	&	ADC1  CH2 (LTC2190) 	\cr
- 
 
 229 
P3	&	1	&	LA17	&	ADC2 CH1 (LTC2271)	\cr
- 
 
 230 
P3	&	2	&	LA15	&	ADC2 CH2 (LTC2271)	\cr
- 
 
 231 
}
- 
 
 232 
\caption/t miniSAS (FMC2DIFF01A J7) signal connections between modules.
- 
 
 233 
\endinsert
- 
 
 234 
 
218 
SPI interface is used by unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back are not possible, thus configuration written to registers in ADC module cannot be validated. We do not observe any problem with this system, but it may be possible source of failures.
235 
SPI interface is used by unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back are not possible, thus configuration written to registers in ADC module cannot be validated. We do not observe any problem with this system, but it may be possible source of failures.
219 
 
 236 
 
- 
 
 237 
\midinsert \clabel[SPI-system]{Grabber binary output format}
- 
 
 238 
\ctable {ccc}
- 
 
 239 
{
- 
 
 240 
SPI connection J7	&	FMC signal	&	Connected to	\cr
- 
 
 241 
SAS-AUX1	 &	LA14\_N	&	SPI DOUT	\cr
- 
 
 242 
SAS-AUX2	 &	LA14\_P	&	SPI CLK	\cr
- 
 
 243 
SAS-AUX3	 &	LA12\_N	&	CE ADC1	\cr
- 
 
 244 
SAS-AUX4	 &	LA12\_P	&	CE ADC2	\cr
- 
 
 245 
SAS-AUX5	 &	LA13\_N	&	soldered to GND	\cr
- 
 
 246 
SAS-AUX6	 &	LA13\_P	&	not used	\cr
- 
 
 247 
SAS-AUX7	 &	LA09\_N	&	not used	\cr
- 
 
 248 
SAS-AUX8	 &	LA09\_P	&	soldered to GND	\cr
- 
 
 249 
}
- 
 
 250 
\caption/t SPI system interconnections
- 
 
 251 
\endinsert
- 
 
 252 
 
- 
 
 253 
 
- 
 
 254 
\midinsert \clabel[clock-interconnections]{Grabber binary output format}
- 
 
 255 
\ctable {lccc}
- 
 
 256 
{
- 
 
 257 
Signal	&	FMC signal	&	FMC2DIFF01A	&	ADCdual01A	\cr
- 
 
 258 
DCO	&	CLK1\_M2C	&	J5-1	&	J13-1	\cr
- 
 
 259 
FR	&	LA18\_CC	&	J10-1	&	J12-1	\cr
- 
 
 260 
ENC	&	LA01\_CC	&	J2-1(PECL OUT)	&	J3-1	\cr
- 
 
 261 
SDGPSDO01A LO	&	CLK0\_M2C	&	J3-1 (PECL IN)	&	N/A	\cr
- 
 
 262 
}
- 
 
 263 
\caption/t Clock system interconnections
- 
 
 264 
\endinsert
- 
 
 265 
 
- 
 
 266 
 
- 
 
 267 
 
220 
\secc FPGA function
268 
\secc FPGA function
221 
 
 269 
 
222 
Several tasks are performed by FPGA. Firstly FPGA prepares sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules after opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself. Last block is activated after ADC configuration.
270 
Several tasks are performed by FPGA. Firstly FPGA prepares sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules after opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself. Last block is activated after ADC configuration.
223 
 
 271 
 
224 
Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which tranfers data from FPGA registers to host PC. Data appears in system device file  "/dev/xillybus_data2_r" on host computer. Binary data which appears in this file after opening are described in table \ref[xillybus-interface].
 272 
Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which tranfers data from FPGA registers to host PC. Data appears in system device file  "/dev/xillybus_data2_r" on host computer. Binary data which appears in this file after opening are described in table \ref[xillybus-interface].