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ADCdual01A module has several digital data output formats. Distinction between these  modes are in number of differential pairs use

ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used

All of these modes are supported by module design. For discussed data acquisition system the 1-lane mode was selected. 1-lane mode allows minimal number of differential pairs between ADCdual01A and FPGA. Digital signaling scheme used in 1-lane mode is shown in image \ref[1-line-out]. 

All of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in 1-lane mode is shown in the following image \ref[1-line-out]. 

\caption/f Digital signaling schema for 1-line ADC digital output mode.

\caption/f Digital signalling schema for 1-line ADC digital output mode.

ADCdual01A parameters can be set either by jumper setup (referred as parallel programming  in device's data sheet) or by SPI interface. SPI interface has been selected for our system, because parallel programming lacks of options (test pattern output setup for example). 

ADCdual01A parameters can be set either by jumper setup (referred to as a parallel programming  in the device's data sheet) or by SPI interface. SPI interface has been selected for our system, because of the parallel programming lack of options (test pattern output setup for example). 

Lengths of differential pairs routed on PCB of module are not matched between pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless signals within differential pairs itself are matched for length. Internal signal traces length mating of differential pairs is mandatory in order to avoid dynamic logic hazard conditions on digital signals. Thus clocks signals are routed most precisely on all designed boards.

Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal tracing of the length matchting of differential pairs is mandatory in order to avoid a dynamic logic hazard conditions on digital signals. Thus clocks' signals are routed in the most precise way on all designed boards.

SPI interface is used by unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back are not possible, thus configuration written to registers in ADC module cannot be validated. We do not observe any problem with this system, but it may be possible source of failures. 

SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures. 

Several tasks are performed by FPGA. Firstly FPGA prepares sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules after opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself. Last block is activated after ADC configuration. 

Several tasks in our design are performed by FPGA. Firstly, FPGA prepares a sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously compared to other logical circuits. The second block is a SPI configuration module, which sends the content of configuration registers to the ADC modules after opening of Xillybus interface file. The third block represents the main module which resolves ADC - PC communication itself. The last block is activated after ADC configuration. 

Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which tranfers data from FPGA registers to host PC. Data appears in system device file  "/dev/xillybus_data2_r" on host computer. Binary data which appears in this file after opening are described in table \ref[xillybus-interface].

Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named  "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface].

We use Gnuradio software to read the data stream from the ADC drive. Gnuradio suite consist of gnuradio-companion which is a graphical tool for creating signal-flow graphs and generating flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view the data stream output from ADC modules. 

In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion which is a graphical tool for creating signal-flow graphs and generating flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view the data stream output from ADC modules. 

Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. 

The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. 

ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]

Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]

Where is 

Where the letters stand for: 

  * $A$ -  Gain of input amplifier.

  * $A$ -  Gain of an input amplifier.

We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply $A = 0.815$. That value of A is confirmed by measurement. 

We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A is further confirmed by the measurement. 

In our measurement setup we have H1012 Ethernet transformer connected at inputs of ADC. Transformer has 10\% tolerance in impedance and amplification. We measured ADC saturation voltage 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated transformer gain. 

In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. The transformer has a 10\% tolerance in impedance and amplification. We measured ADC saturation voltage of 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated transformer gain. 

For ADC2 we must use formula with different constant \ref[ADC1-gain]. ADC2 module has LT6600-2.5 populated and gain is $A = 2.457$ with same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.   

For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.   

Where is 

Where the letters stand for:

  * $A$ -  Gain of input amplifier.

  * $A$ -  Gain of an input amplifier.

Computed FFT spectra for measured signal are shown in images \ref[ADC2-FFT] and \ref[ADC1-FFT].  Both images confirms that ADCdual01A modules have input dynamical range 80 dB at least. 

Computed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT].  Both images confirm that ADCdual01A modules have input dynamical range of 80 dB at least. 

For additional validation of system design a receiver setup was constructed. 

For additional validation of system characteristics a receiver setup has been constructed. 

Interferometry station was selected as most basic setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematic of used setup is shown in image \ref[block-schematic]. Two ground-plane antennas were used and mounted outside of balcony at CTU building at location 50$^\circ$ 4\' 36.102\" N,  14$^\circ$ 25\' 4.170\" E. 

Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4\' 36.102\" N,  14$^\circ$ 25\' 4.170\" E. 

Antennas were equipped  by LNA01A amplifiers. Coaxial cable length are matched for 5 meters. And antennas were isolated by common mode ferrite bead mounted on cable for minimize signal coupling between antennas. Evaluation system consists SDGPSDO local oscillator subsystem used for tuning local oscillator frequency. 

Antennae were equipped  by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency.