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 \chap Testing construction
-Whole design of radioastronomy receiver digitalization unit shoud be constructed for the most universal application in signal digitalisation from radioastronomy receivers. Ilustrating problem for its use is signal digitalisation from multiple antenna arrays. This design will be used as part of MLAB Advanced Radio Astronomy System.
+Whole design of radioastronomy receiver digitalization unit is constructed for use in wide range of applications and tasks related to signal digitalisation from radioastronomy receivers. Illustrating problem for its use is signal digitalisation from multiple antenna arrays. And this design will become a part of MLAB Advanced Radio Astronomy System.
 \sec Required parameters
 Wide dynamical range and high  3 intercept point are desired. The receiver must accept wide dynamic signals because classic radioastronomy signal in typically weak signal covered by strong man made noise signal.
 Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it.  This central oscillator has software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design was developed in parallel to this diploma thesis construction as related project, but it is not explicitly required by specification.}
  This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.
 Every ADC module will be directly connected to CLKHUB02A module. This module takes sampling clock delevered by FPGA from main local oscillator.  This signal should use high quality differential signaling cable -- SATA cable should be used for this purpose.
-\secc Signal connectors
+\secc Signal cable connectors
 Several widely used and commercially easily accessible differential connectors were considered.
 \begitems
 * HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
 * SATA  		%{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
 * DisplayPort 		%[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
 * SAS/miniSAS
 \enditems
-MiniSAS connector was chosen as  the best for use in connection multiple ADC modules.  This miniSAS connector is compatible with existing SATA cabling system and agregates multiple SATA cables to single connector. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems thus is commercially available.
+MiniSAS connector was chosen as  the best for use in connection multiple ADC modules.  This miniSAS connector is compatible with existing SATA cabling system and aggregates multiple SATA cables to single connector this cable type is shown on image \ref[img-miniSAS-cable]. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable. This cable is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems thus is commercially available.
-One drawback is that miniSAS PCB connectors are mainufactured in SMT versions only. But outer metal housing of connector is standard trough hole type. This mechannical design should degrade durability of this connector type.
+One drawback is that miniSAS PCB connectors are manufactured in SMT versions only. But outer metal housing of connector is standard trough hole type. This mechanical design should degrade durability of this connector type.
 \midinsert
+\clabel[img-miniSAS-cable]{Used miniSAS cable}
 \picw=10cm \cinspic ./img/miniSAS_SATA_cable.jpg
 \caption/f A type of miniSAS cable similar to used.
 \endinsert
+\secc Signal integrity requirements
+Used ADC modules has DATA clock frequency eight times higher than sampling frequency in single line output mode. This implicates 40 MHz output bit rate.
 \secc Design of ADC modules
 This modules have MLAB standard construction with four mounting holes in corner aligned in defined raster.
-Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel.  This signal concept enables selection of proper bus bitwidth according to sampling rate. (Higher bus bitwidth downgrades signaling speed and vice versa.)
+Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel.  This signal concept enables selection of proper bus bitwidth according to sampling rate. (Higher bus bit-width downgrades signalling speed and vice versa.)
 For connection of this signaling layout, miniSAS to multiple SATA cable should be used.
 For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad.  And much better than widely used Eagle software.
   * serial LVDS
 \enditems
 Serial LVDS has been selected because uses lowest number of differencial pairs. This parameter is mandatory for construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}
-An ultrasound AFE chips should be ideal for this purpose -- this chips has front-end amplifiers and filters integrated. But theirs drawback is incapability of handling differential input signal and relatively low dynamic range (consists 12bit ADC). This IO has many ADC channels thus scalling are possible in factor of 4 receivers (8 analog channels).
+An ultrasound AFE chips should be ideal for this purpose -- this chips has front-end amplifiers and filters integrated. But theirs drawback is incapability of handling differential input signal and relatively low dynamic range (consists 12bit ADC). This IO has many ADC channels thus scaling are possible in factor of 4 receivers (8 analogue channels).
-If we require separate output for every analog channel and 16bit deph. Only several ADCs currently exists which meet these requirements.
+If we require separate output for every analogue channel and 16bit deph. Only several 2-Channel simultaneous sampling ADCs currently exists which meet these requirements.  These ADCs parameters are summarised in table \ref[ADC-type]
+\midinsert \clabel[ADC-types]{Available ADC types}
-\begitems
+\ctable{lrrrrrcc}{
+\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
+SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
+SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr
+S/H Bandwidth [MHz] & 200 & \multispan6 550 \cr
+Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 &  105 & 125 \cr
+Configuration & \multispan7 SPI \cr
-*[[http://www.linear.com/product/LTC2271|LTC2271]]
+Package & \multispan7 52-Lead (7mm $×$ 8mm) QFN \cr
+}
-*[[http://www.linear.com/product/LTC2191|LTC2190-2195]].
+\caption/t Summary of available ADC types and theirs parameters.
-\enditems
+\endinsert
 All parts in this category are compatible with one board layout. Main differences are in sampling frequency and signal to noise ratio. The slowest one has maximal sampling frequency 20 MHz. But all types have minimal sampling frequency 5 MSPS.  All types were configurable over serial interface (SPI).  SPI seems to be a standard for high-end ADC chips from main manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
 \secc ADC modules interface
 \secc Output data format
 \midinsert
-\ctable {cccccccccc}{
+\ctable {clllllllll}{
 \hfil
  & \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
 Data name &  FRAME  & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2  \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil  \cr
 Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
 Content & saw signal & $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ \cr
 Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal.
 \secc ADC module parameters
 Two pieces of ADC module design were realised and tested first piece denoted as ADC1 has LTC21190
-ADC chip populated with LT660015 front-end operational apmlifier. This ADC1 module has 1kOhm resistors populated on inputs which gives to module internal attenuation of input signal. Value of this attenuation is described by formula
+ADC chip populated with LT660015 front-end operational apmlifier. This ADC1 module has 1kOhm resistors populated on inputs which gives to module internal attenuation of input signal. Value of this attenuation $A$ is described by formula
+$$
+A = {1580 \times R_1} \over {R_1 + R_2}
+$$
 \midinsert
 \picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
 \caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.
 \endinsert
 Parallella is gon
 \sec GPU based computational system
+A new GPU development board NVIDIA K1 has been released in recent time it is shown on image \ref[img-NVIDIA-K1]. This board are intended for use in computer vision, robotics, medicine, security, and automotive. This board has ideal parameters for signal processing for this relatively low price 192 USD.  But it is currently in pre-order release stage (in April 2014).
+\midinsert
+\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
+\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
+\caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}.
+\endinsert
 \chap Conclusion
 Special design of scalable data-aquisition system was proposed. This system has parameters

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