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   * Support for any number of receivers in range 1 to 8
 \enditems
 \sec Sampling frequency
-Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1 MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
+Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1$\ $MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
-We calculate minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of real writing speed o classical HDD and it is almost double of real bandwidth of USB 2.0 interface.
+We calculate minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of real writing speed o classical HDD and it is almost double of real bandwidth of USB 2.0 interface.
 \sec System scalability
 For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires.
-Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.).
+Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.). If more robustness is required from designs DCO and FR signal may be collected from other modules and routed through an voting logic which will correct possible signal defects.
 This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
 \secc Differential signaling
 \secc Phase matching
 For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows precise high resolution imaging of objects.
-High phase stability in our scalable design is achieved through centralized frequency generation  and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices.
+High phase stability in our scalable design is achieved through centralized frequency generation  and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has advantage over LVDS in signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. Consumption currents of LVPECL logic are near constant over operating frequency range due to use of bipolar transistor this minimises voltage glitches which are typical for CMOS logic. One drawbacks of that parameters is high power consumption of LVPECL logic.
 This design ensures that all devices have access to the defined phase and known frequency.
 \sec System description
 \secc Frequency synthesis
 We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
 We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging.
-GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source ... are summarized in table \ref[LO-noise].
+GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source \cite[si570-chip] are summarized in table \ref[LO-noise].
 \midinsert \clabel[LO-noise]{Available ADC types}
 \ctable{lcc}{
 	&	 \multispan2 \hfil Phase Noise [dBc/Hz] \hfil 		\cr
 \endinsert
 \secc Signal integrity requirements
 \label[diff-signaling]
-We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4*10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our design.
+We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our current design operated on lowest sampling speed. Length matching becomes critical in future version with higher sampling rates, then cable length must be matched. However SATA cabling technology is prepared for that case and matched SATA cables are standard merchandise.
 \secc ADC modules design
 \secc ADC selection
 An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels).
 If we require a separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements.  We have summarized the ADCs in the following table \ref[ADC-type]
 \midinsert \clabel[ADC-types]{Available ADC types}
-\ctable{lrrrrrcc}{
+\ctable{lccccccc}{
 \hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
 SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
 SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr
 S/H Bandwidth [MHz] & 200 & \multispan6 550 \cr
 Sampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 &  105 & 125 \cr
 \clabel[VITA57-regions]{VITA57 board geometry}
 \picw=10cm \cinspic ./img/VITA57_regions.png
 \caption/f Definition of VITA57 regions.
 \endinsert
 Several SATA connectors and two miniSAS connectors are populated on this board.  This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
 Lengths of differential pairs routed on PCB of module are not matched between pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless signals within differential pairs itself are matched for length. Internal signal traces length mating of differential pairs is mandatory in order to avoid dynamic logic hazard conditions on digital signals. Thus clocks signals are routed most precisely on all designed boards.
 Signal configuration used in our trial design is described in the following tables.
-\secc Output data format
+%% zapojeni SPI, FPGA zpatky necte konfiguraci, ale je tam na slepo nahravana.
+SPI interface is used by unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back are not possible, thus configuration written to registers in ADC module cannot be validated. We do not observe any problem with this system, but it may be possible source of failures.
+\secc FPGA function
+Several tasks are performed by FPGA. Firstly FPGA prepares sampling clock for ADCdual01A modules this task is separate block in FPGA and runs asynchronously to other logic. Second block is SPI configuration module, which sends configuration words to ADC modules after opening of Xillybus interface file. Third block is main module, which resolve ADC - PC communication itself. Last block is activated after ADC configuration.
-\midinsert
+Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which tranfers data from FPGA registers to host PC. Data appears in system device file  "/dev/xillybus_data2_r" on host computer. Binary data which appears in this file after opening are described in table \ref[xillybus-interface].
+\midinsert \clabel[xillybus-interface]{Grabber binary output format}
 \ctable {clllllllll}{
 \hfil
  & \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
 Data name &  FRAME  & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2  \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil  \cr
 Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
 Content & saw signal & $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ \cr
+}
 \caption/t System device "/dev/xillybus_data2_r" data format
 \endinsert
-\sec Achieved parameters
+Detailed description of FPGA function can be found in \cite[fpga-middleware]
 \secc Data reading and recording
 We use Gnuradio software to read the data stream from the ADC drive. Gnuradio suite consist of gnuradio-companion which is a graphical tool for creating signal-flow graphs and generating flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view the data stream output from ADC modules.
 \caption/f User interface window of a running ADC grabber.
 \endinsert
 Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal.
+\sec Achieved parameters
 \secc ADC module parameters
 Two pieces of ADC modules were completed and tested. The first piece, labeled ADC1, has LTC2190
 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]
 \label[ADC1-gain]
 $$
-A = {806 \times R_1 \over R_1 + R_2}
+A = {806 \cdot R_1 \over R_1 + R_2}
 $$
 Where is
 \begitems
   * $A$ -  Gain of input amplifier.
 For ADC2 we must use formula with different constant \ref[ADC1-gain]. ADC2 module has LT6600-2.5 populated and gain is $A = 2.457$ with same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.
 \label[ADC2-gain]
 $$
-A = {1580 \times R_1 \over R_1 + R_2}
+A = {1580 \cdot R_1 \over R_1 + R_2}
 $$
 Where is
 \begitems
   * $A$ -  Gain of input amplifier.
 \clabel[block-schematic]{Receiver block schematic}
 \picw=10cm \cinspic ./img/Coherent_UHF_SDR_receiver.png
 \caption/f Complete receiver block schematic of dual antenna interferometric station.
 \endinsert
+% doplnit schema skutecne pouziteho systemu
+Despite of schematic diagram proposed on beginning of system description....
+We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer.
+Reason for this modification is simplification of frequency tuning during experiment. It is because single oscillator may be used only with proper setting of FPGA divider, this divider may be modified only by recompilation of FPGA code and loading/flashing new FPGA schema. Due to fact that FPGA was connected to PCI express and kernel drivers and hardware must be reinitialized, reboot of PC is required.  Instead of this procedure, we set the FPGA divider to constant division of factor 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
 \midinsert
 \clabel[meteor-reflection]{Meteor reflection}
 \picw=10cm \cinspic ./img/screenshots/observed_meteor.png
 \clabel[phase-phase-difference]{Phase difference}
 \picw=10cm \cinspic ./img/screenshots/phase_difference.png
 \caption/f Demonstration of phase difference between antennas.
 \endinsert
+We use ACOUNT02A device for frequency checking on both local oscillators.
 %\sec Simple passive Doppler radar
 %\sec Simple polarimeter station
 The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially  constructed ASICs are used for this task.
 \sec Custom design of FPGA board
-In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of this board to another adapter board with PCIe we expect a use of a host interface.
+In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface.
-Thunderbolt technology standard was expected to be used in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution.
+Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform.
-However, these systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis.
+However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis.
 Therefore, a better solution probably needs to be found.
+An interfacing problem will by  probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to increased demand of embedded technologies, which requires high computation capacity, low power consumption and small size -- especially smart phones. Many of those ARM based systems has interesting parameters for signal processing. This facts makes Intel's ix86 architecture unattractive for future project.
 \sec Parralella board computer
-%Parallella is gon
+Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores,  Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM,  85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. Completely  this board provides  In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running.
+\midinsert
+\clabel[img-parallella-board]{Parallella board overview}
+\picw=15cm \cinspic ./img/ParallellaTopView31.png
+\caption/f Top view on Parallella-16 board \cite[parallella16-board].
+\endinsert
+If Parallella board will be used a new ADC interface board should be designed. Interfacing module will use four PEC connectors mounted on bottom of Parallella board. This doughter module should have MLAB compatible design preferably constructed as separable module for every Parallella's PEC connectors.
+Main imperfections of Parallella board is unknown lead time and absence of onboard data
 \sec GPU based computational system
 A new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have ideal parameters for signal processing for a relatively low price of 192 USD.  Unfortunately, they are currently only in pre-order release stage (in April 2014).

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