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This design ensures that all system devices have access to the defined phase and the known frequency.
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This design ensures that all system devices have access to the defined phase and the known frequency.
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\sec System description
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\sec System description
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This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed. Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consist antennas equipped by
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This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed.
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\secc Receiver overview
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%% dopsat celkovy popis systemu.
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Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consists of antennas equipped by preamplifier (LNA) and optionally by band pass filter (BPF). The signal is conducted to down-converting mixers after amplification. Mixers are connected to precise local oscillator (GPSDO01A) controlled from PC by I$^2$C bus. Down-converted signal is digitized by ADCdual01A modules. The ADC modules are connected using FMC2DIFF01A adapter board to data concentrator realized by FPGA board.
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In this thesis, the ADC module, adapter board, FPGA specification is proposed. The other modules of the receiver system are currently existing.
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\midinsert
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\midinsert
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\clabel[expected-block-schematic]{Expected system block schematic}
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\clabel[expected-block-schematic]{Expected system block schematic}
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\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
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\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
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\par\nobreak \vskip\wd0 \vskip-\ht0
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\par\nobreak \vskip\wd0 \vskip-\ht0
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