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Sampling frequency is limited by technical constrains in testing construction design. This parameter is especially limited by sampling frequencies of analog to digital conversion chips accessible on market. Combination of required parameters -- dynamic range which needs 16bit at least and minimum sampling frequency of 1 MSPS, leads to high end ADC chips. Which does not support such low sampling frequencies at all. Its minimum sampling frequency is 5 MSPS.  

For analog channels scalability special parameters of ADC modules were needed. ADC module ideally needs separate output for each I/Q channel. ADC module must have separate inputs for sampling and for data output clocks. This parameters allows conduction of relatively low digital data rates. And digital signal can be conducted on long wires. 

Clock signal will be handled specially in this scalable design. Selected ADC chip guaranteed defined clock skew between sampling and data output clock. This allows taking data and frame  clocks from first ADC module only. Other data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.)   

This system concept allows scalability technically  limited by number of differential signals on host side,  and its computational power.  There is another advantage of scalable data acquisition system -- economic reasons. Observatories or end user can pick choice how much money they are able to spent in radioastronomy receiver system. This option is especially useful for science sites without previous experience with radioastronomy observations.     

This concept of scalable design requires relatively long traces between ADC and digital unit which captures the data and performs computations.  Distance of digital processing unit and analog to digital conversion unit has advantage in noise retention typically produced by digital circuits. Those digital circuits such as FPGA or other flip-flops block and traces usually works on high frequencies and emits wideband noise with relatively low power.  In such case any distance increase between noise source and analog signal source increase S/N significantly. But this distance also brings problems with digital signal transmission between ADC and computational unit. But this obstruction should be resolved easier in free space than on board routing. The high quality differential signalling shielded cables should be used.  This technology have two advantages on PCB signal routing. It can use two wire twisting for leak inductance suppression of signal path. And this twisted pair may be additionally shielded by uninterrupted metal foil.              

In this section testing system will be described.

Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it.  This central oscillator has software defined GPS disciplined control loop for frequency stabilisation. This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.  

Several ADC module imperfections such as useless separation of FRAME and DCO signal to two connectors should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest. 

Construction of final system which should be used for real radioastronomy observations will be described. This chapter is mainly theoretical analysis of systems which should be used for data handling. 

\sec Custom design of FPGA board

\sec Parralella board computer

Parallella is gon

\sec GPU based computational system