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\secc Frequency synthesis
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\secc Frequency synthesis
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging.
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging.
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GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source ... are summarised in table \ref[LO-noise].
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GPSDO device consists the Si570 chip with LVPECL output. Phase jitter of GPSDO is determined mainly by Si570 phase noise. Parameters of used Si570 from source ... are summarized in table \ref[LO-noise].
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\midinsert \clabel[LO-noise]{Available ADC types}
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\midinsert \clabel[LO-noise]{Available ADC types}
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\ctable{lcc}{
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\ctable{lcc}{
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& \multispan2 Phase Noise [dBc/Hz] \cr
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& \multispan2 \hfil Phase Noise [dBc/Hz] \hfil \cr
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Offset Frequency & $F_out$ 156.25 MHz & $F_out$ 622.08 MHz \cr
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Offset Frequency & $F_{out}$ 156.25 MHz & $F_{out}$ 622.08 MHz \cr
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100 [Hz] & –105 & –97 \cr
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100 [Hz] & –105 & –97 \cr
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1 [kHz] & –122 & –107 \cr
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1 [kHz] & –122 & –107 \cr
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10 [kHz] & –128 & –116 \cr
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10 [kHz] & –128 & –116 \cr
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100 [kHz] & –135 & –121 \cr
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100 [kHz] & –135 & –121 \cr
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1 [MHz] & –144 & –134 \cr
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1 [MHz] & –144 & –134 \cr
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose. FPGA may slightly affect clock signal quality by additive noise, but has negligible effect in application where developed system will be used.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator. This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose. FPGA may slightly affect clock signal quality by additive noise, but has negligible effect in application where developed system will be used.
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram.
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram.
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Time-marking should be improved in future by digitalisation GPS signal directly with dedicated ADC channel. Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information.
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Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. GPS signal can be then directly sampled by dedicated receiver an separate ADC module. Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information.
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\secc Signal cable connectors
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\secc Signal cable connectors
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
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\endinsert
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\endinsert
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\secc Signal integrity requirements
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\secc Signal integrity requirements
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\label[diff-signaling]
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\label[diff-signaling]
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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4*10^7 = 25$ ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3*sample time$ time which is 1.485 m. Therefore length matching is not critical in our design.
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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4*10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore length matching is not critical in our design.
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- |
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\secc ADC modules design
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\secc ADC modules design
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\secc ADC selection
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\secc ADC selection
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A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad, the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
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A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad, the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
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As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
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As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
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ADCdual01A module has several digital data output formats
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ADCdual01A module has several digital data output formats. Distinction between these modes are in number of differential pairs use
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\begitems
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\begitems
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* 1-lane mode
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* 1-lane mode
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* 2-lane mode
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* 4-lane mode
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\enditems
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\enditems
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All of these modes are supported by module design. For discused data acquisition system the 1-lane mode was selected. 1-lane mode allows minimal number of differential pairs between ADCdual01A and FPGA. Digital signaling scheme used in 1-lane mode is shown in image \ref[1-line-out].
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All of these modes are supported by module design. For discussed data acquisition system the 1-lane mode was selected. 1-lane mode allows minimal number of differential pairs between ADCdual01A and FPGA. Digital signaling scheme used in 1-lane mode is shown in image \ref[1-line-out].
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\midinsert
|
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\midinsert
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| 168 |
\clabel[1-line-out]{Single line ADC output signals}
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\clabel[1-line-out]{Single line ADC output signals}
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| 169 |
\picw=15cm \cinspic ./img/ADC_single_line_output.png
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169 |
\picw=15cm \cinspic ./img/ADC_single_line_output.png
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| 170 |
\caption/f Digital signaling shema for 1-line ADC digital output mode.
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\caption/f Digital signaling schema for 1-line ADC digital output mode.
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\endinsert
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\endinsert
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ADCdual01A parameters can be set either by jumper setup (refered as parallel programming in device's data sheet) or by SPI interface. SPI interface has been selected for our system, because parallel programming lacks of options (test pattern output setup for example).
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ADCdual01A parameters can be set either by jumper setup (referred as parallel programming in device's data sheet) or by SPI interface. SPI interface has been selected for our system, because parallel programming lacks of options (test pattern output setup for example).
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Complete schematic diagram of ADCdual01A module board is included in the appendix.
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Complete schematic diagram of ADCdual01A module board is included in the appendix.
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\secc ADC modules interface
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\secc ADC modules interface
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Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
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180 |
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
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This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
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181 |
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
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182 |
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The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realised without the use of massive RFI mitigation techniques).
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183 |
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
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| 184 |
Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
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184 |
Differential signaling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
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185 |
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\midinsert
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186 |
\midinsert
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| 187 |
\picw=10cm \cinspic ./img/ML605-board.jpg
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187 |
\picw=10cm \cinspic ./img/ML605-board.jpg
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| 188 |
\caption/f FPGA ML605 development board.
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188 |
\caption/f FPGA ML605 development board.
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| 189 |
\endinsert
|
189 |
\endinsert
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