Subversion Repositories svnkaklik

Wide dynamical range and high 3 intercept points are desired. The receiver must accept wide dynamic signals because a typical radioastronomy signal has a form of a weak signal covered by a strong man-made noise signal.    

Wide dynamical range and high 3 intercept points are desired. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise.    

Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market. Combination of the required parameters -- dynamic range which needs at least 16bit and a minimum sampling frequency of 1 MSPS, leads to high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.  

Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1 MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.  

For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ADC module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. Then the digital signal can be conducted even through long wires. 

For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ADC module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. 

Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes. (Failure detection, jitter measurement etc.)   

Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.).

This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.     

This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.     

The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such case any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology have two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Moreover, the twisted pair may additionally be shielded by uninterrupted metal foil.              

The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.              

For multiple antenna radioastronomy projects, system phase stability is mandatory. It allows precise high resolution imaging of objects. 

For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows precise high resolution imaging of objects. 

High phase stability in our scalable design is achieved by centralised frequency generation  and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices. 

High phase stability in our scalable design is achieved through centralised frequency generation  and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices. 

This design ensures that all devices have access to defined phase and known frequency.     

This design ensures that all devices have access to the defined phase and known frequency.     

We have used centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used while other working frequencies have been derived by its division. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by specification.}

We have used a centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used, while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}

 Frequency monitoring compensation method has been used in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability on wide area for effective radioastronomy imaging. 

We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging. 

Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock delivered by FPGA from main local oscillator.  This signal should use high quality differential signalling cable -- SATA cable should be used for this purpose. 

Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. 

Several widely used and commercially easily accessible differential connectors were considered. 

Several widely used and commercially easily accessible differential connectors were considered to be use in our design. 

MiniSAS connector was chosen as  the best to be used in connecting multiple ADC modules.  The miniSAS connector is compatible with existing SATA cabling system and aggregates multiple SATA cables to a single connector this cable type is shown on image \ref[img-miniSAS-cable]. Translation between SATA and miniSAS is achieved by SAS to SATA adapter cable which is used in servers to connecting SAS controller to multiple SATA hard disc in RAID systems thus is commercially available. 

At the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It can be seen on the following picture \ref[img-miniSAS-cable]. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. 

One drawback is that miniSAS PCB connectors are manufactured in SMT versions only. But outer metal housing of connector is standard trough hole type. This mechanical design should degrade durability of this connector type. 

The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. The outer metal housing of connector is designed to be mounted using a standard through-hole mounting scheme, a design that unfortunately decreases the durability of the connector. 

Used ADC modules has DATA clock frequency eight times higher than sampling frequency in single line output mode. This implicates 40 MHz output bit rate. 

We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. 

\secc Design of ADC modules

\secc ADC modules design

This modules have MLAB standard construction with four mounting holes in corner aligned in defined raster. 

The ADC modules have a standard MLAB construction scheme with four mounting holes in corners aligned in defined raster. 

Data serial data output of ADC module should be connected directly to FPGA for basic primary signal processing. Used ADC chip has selectable bit width of data output bus thus output SATA connectors has signals arranged to contain a single bit from every ADC channel.  This signal concept enables selection of proper bus bit-width according to sampling rate. (Higher bus bit-width downgrades signalling speed and vice versa.)

Data serial data outputs of ADC modules should be connected directly to FPGAs for the basic primary signal processing. The ADC chip used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel.  This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)

For connection of this signalling layout, miniSAS to multiple SATA cable should be used.  

In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used.  

For PCB layout KiCAD design suite was used. Used version has the CERN Push \& Shove routing capability integrated but was slightly unstable and sometimes falls on exception during routing. Design must be often saved due to this stability issues. But Open-source KiCAD works well compared to commercial solutions as MentorGraphics PADS or Cadence Orcad.  And much better than widely used Eagle software.

A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad,  the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.

New PCB footprints have been designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. And they are now publicly accessible from official KiCAD repository at GitHub.  

As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.  

Several ADC signalling formats currently exist for communication with FPGA. 

There exist several ADC signalling formats currently used in communication with FPGA. 

Serial LVDS has been selected because uses lowest number of differencial pairs. This parameter is mandatory for construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}

Because it uses the smallest number of differential pairs, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}

An ultrasound AFE chips should be ideal for this purpose -- this chips has front-end amplifiers and filters integrated. But theirs drawback is incapability of handling differential input signal and relatively low dynamic range (consists 12bit ADC). This IO has many ADC channels thus scaling are possible in factor of 4 receivers (8 analogue channels).

An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels).

If we require separate output for every analogue channel and 16bit deph. Only several 2-Channel simultaneous sampling ADCs currently exists which meet these requirements.  These ADCs parameters are summarised in table \ref[ADC-type] 

If we require a separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements.  We have summarised the ADCs in the following table \ref[ADC-type] 

\caption/t Summary of available ADC types and theirs parameters. 

\caption/t The summary of available ADC types and theirs characteristics. 

All parts in this category are compatible with one board layout. Main differences are in sampling frequency and signal to noise ratio. The slowest one has maximal sampling frequency 20 MHz. But all types have minimal sampling frequency 5 MSPS.  All types were configurable over serial interface (SPI).  SPI seems to be a standard for high-end ADC chips from main manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..). 

All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..). 

All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3. 

Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support zone 1 and zone 3. 

This specification guarantee compatibility with others FPGA board which has FMC LPC connector for Mezzanine Card. Schematic diagram of this adapter board is included in appendix. 

This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of this adapter board is included in the appendix. 

Primary purpose of this PCB is to enable connection of ADC modules from space excluded from PC case.  (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques). 

The primary purpose of the PCB is to enable the connection of ADC modules from space excluded from PC case.  (In PC box analog circuits cannot be realised without using of massive RFI mitigation techniques). 

Differential signaling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality.  

Differential signalling connectors should be used for conducting digital signal over relatively long cable. Signalintegrity sensitive links (clocks) are equiped by output driver and translator to LVPECL logic for better signal transmission quality.