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\chap Trial version of the receiver, design and implementation
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\chap Trial version of the digitizer
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The whole design of the radioastronomic receiver digitization unit is meant to be used in a wide range of applications and tasks related to digitization of a signal. A good illustrating problem for its use is the signal digitization from multiple antenna arrays.
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The whole design of the radioastronomic receiver digitization unit is meant to be used in a wide range of applications and tasks related to digitization of a signal. A good illustrating problem for its use is the signal digitization from multiple antenna arrays. Design and implementation of the system is presented in this chapter.
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\midinsert
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\midinsert
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\clabel[expected-block-schematic]{Expected system block schematic}
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\clabel[expected-block-schematic]{Expected system block schematic}
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\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
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\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
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\par\nobreak \vskip\wd0 \vskip-\ht0
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\par\nobreak \vskip\wd0 \vskip-\ht0
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\noindent
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\noindent
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We analyze several of the parameters more in detail in the sequel.
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We analyze several of the parameters more in detail in the sequel.
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\sec Sampling frequency
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\sec Sampling frequency
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The sampling frequency has not been a limiting factor in the trial version. Generally, the sampling frequency is mostly limited by the sampling frequencies of the analog-to-digital conversion chips available on the market and by the interface bandwidth. The combination of required parameters -- dynamic range needing 16 bits  at least and a minimum sampling frequency of 1 Mega-Samples Per Second (MSPS\glos{MSPS}{Mega-Samples Per Second}) -- leads to the need of the high-end ADC chips. However, they do not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.
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The sampling frequency has not been a limiting factor in the trial version. Generally, the sampling frequency is mostly limited by the sampling frequencies of the analog-to-digital conversion chips available on the market and by the interface bandwidth. The combination of required parameters -- dynamic range needing 16 bits  at least and a minimum sampling frequency of 1 Mega-Samples Per Second (MSPS\glos{MSPS}{Mega-Samples Per Second}) -- leads to the need of the high-end ADC chips. However, they support minimum sampling frequency 5$\ $MSPS.
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We calculated the minimal data bandwidth data rate for eight receivers, 2~bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/sec. Such a data rate is at the limit of the actual writing speed of a classical hard disk drive (HDD\glos{HDD}{Hard disk drive}) and it is almost a double the real bandwidth of USB~2.0\glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts, we must use a faster interface. Such a faster interface is especially needed in cases in which we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate.
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We calculated the minimal data bandwidth rate for eight receivers, 2~bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/sec. Such a data rate is at the limit of the actual writing speed of a classical hard disk drive (HDD\glos{HDD}{Hard disk drive}) and it is almost a double the real bandwidth of USB~2.0\glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts, we must use a faster interface. Such a faster interface is especially needed in cases in which we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate.
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The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express \glos{PCI Express}{Peripheral Component Interconnect Express}  interface as the simplest and the most reliable solution.
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The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express \glos{PCI Express}{Peripheral Component Interconnect Express}  interface as the simplest and the most reliable solution.
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\sec System scalability
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\sec System scalability
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Special parameters of ADC modules are required to secure scalability of analog channels. Ideally, there should be a separate output for each analog channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow the operation at relatively low digital data rates. As a result, the digital signal can be conducted even via long wires. The modular architecture enables the separation from a central logical unit which supports optimization of a number of analog channels.
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Special parameters of ADC modules are required to secure scalability of analog channels. Ideally, there should be a separate output for each analog channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow the operation at relatively low digital data rates. As a result, the digital signal can be conducted even via long wires. The modular architecture enables the separation from a central logical unit which supports optimization of a number of analog channels.
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This system concept allows for scalability, which is limited technically by a number of differential signals on the host side and its computational power.  There is another advantage of the scalable data acquisition system -- an economic one. Observatories or end users can make a choice how much money are they willing to spent on the radioastronomy receiver system. This freedom of choice is especially useful for scientific sites without previous experience in radioastronomy observations.
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This system concept allows for scalability, which is limited technically by a number of differential signals on the host side and its computational power.  There is another advantage of the scalable data acquisition system -- an economic one. Observatories or end users can make a choice how much money are they willing to spent on the radioastronomy receiver system. This freedom of choice is especially useful for scientific sites without previous experience in radioastronomy observations.
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\secc Differential signalling
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\secc Differential signalling
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The above mentioned concept of the scalable design requires a relatively long circuit traces between ADC and the digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has the advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA\glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces, which work usually at high frequencies and emit the wide-band noise with relatively low power. In such cases, any increase in a distance between the noise source and the analog signal source increases S/N significantly. However, at the same time, a long distance introcuces problems with the digital signal transmission between ADC and the computational unit. However, this obstacle should be resolved more easily in a free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA\glos{SATA}{Serial ATA}\glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB\glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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The above mentioned concept of the scalable design requires a relatively long circuit traces between ADC and the digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has the advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA\glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces work usually at high frequencies and emit the wide-band noise with relatively low power. In such cases, any increase in a distance between the noise source and the analog signal source increases S/N significantly. However, at the same time, a long distance introcuces problems with the digital signal transmission between ADC and the computational unit. This obstacle should be resolved more easily in a free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA\glos{SATA}{Serial ATA}\glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB\glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path. Second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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\secc Phase matching
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\secc Phase matching
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The system phase stability is a mandatory condition for multi-antennas radioastronomy projects. It allows a precise, high resolution imaging of objects, increases signal to noise ratios in several observation methods and enables using of advanced algorithms for signal processing.
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The system phase stability is a mandatory condition for multi-antennas radioastronomy projects. It allows a precise, high resolution imaging of objects, increases signal to noise ratios in several observation methods and enables using of advanced algorithms for signal processing.
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The high phase stability is achieved in our scalable design through centralized frequency generation and distribution with multi-output Low Voltage Emitter-coupled logic (LVPECL\glos{LVPECL}{Low Voltage Emitter-coupled logic}) hubs (CLKHUB02A), which have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has the advantage over the Low-voltage differential signaling (LVDS\glos{LVDS}{Low-voltage differential signaling}) in the signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. The power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This arrangement minimizes voltage glitches which are typical for CMOS\glos{CMOS}{Complementary metal–oxide–semiconductor} logic. One drawback of its parameters is a high power consumption of LVPECL logic, which reaches tens of milliamperes per device easily.
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The high phase stability is achieved in our scalable design through centralized frequency generation and distribution with multi-output Low Voltage Emitter-coupled logic (LVPECL\glos{LVPECL}{Low Voltage Emitter-coupled logic}) hubs (CLKHUB02A), which have equiphased outputs for multiple devices. The LVPECL logic is used on every system critical clock signal distribution hub. This logic has the advantage over the Low-voltage differential signaling (LVDS\glos{LVDS}{Low-voltage differential signaling}) in the signal integrity robustness. It uses higher logical levels and higher signalling currents. The power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This arrangement minimizes voltage glitches which are typical for CMOS\glos{CMOS}{Complementary metal–oxide–semiconductor} logic. One drawback of its parameters is a high power consumption of LVPECL logic, which reaches tens of milliamperes per device easily.
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This design ensures that all system devices have access to the defined phase and the known frequency.
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This design ensures that all system devices have access to the defined phase and the known frequency.
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\sec System description
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\sec System description
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This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board]. The board had been used in a previous project and has not been used since. However, the FPGA parameters are more than sufficient of what we need for fast data acquisition system.
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This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed.
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\secc Frequency synthesis
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\secc Frequency synthesis
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO]. The other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS\glos{GPS}{Global Positioning System}  disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma project as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document.}
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator (GPSDO\glos{GPSDO}{GPS disciplined oscillator}) has been used \cite[MLAB-GPSDO]. The other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS\glos{GPS}{Global Positioning System}  disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma project as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document.}
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We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on the radioastronomy equipment, which needs the precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging.
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We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on the radioastronomy equipment, which needs the precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging.
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The GPSDO device consists of Si570 chip with LVPECL output. The phase jitter of the GPS disciplined oscillator (GPSDO\glos{GPSDO}{GPS disciplined oscillator}) is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in Table~\ref[LO-noise] (source \cite[si570-chip] ).
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The GPSDO device consists of Si570 chip with LVPECL output. The phase jitter of the GPS disciplined oscillator is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in Table~\ref[LO-noise] (source \cite[si570-chip] ).
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GPSDO design, which is included in the data acquisition system, has a special feature -- it generates time marks for a precise time-stamping of the received signal. Time-stamps are created by disabling the local oscillator outputs, connected to SDRX01B receivers, for 100 $\mu$s.  As the result, a rectangular click in the ADC input signal is created, which appears as a horizontal line in the spectrogram.
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GPSDO design, which is included in the data acquisition system, has a special feature -- it generates time marks for a precise time-stamping of the received signal. Time-stamps are created by disabling the local oscillator outputs, connected to SDRX01B receivers, for 100 $\mu$s.  As the result, a rectangular click in the ADC input signal is created, which appears as a horizontal line in the spectrogram.
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Time-stamps should be seen in the image in Figure~\ref[meteor-reflection] (above and below the meteor reflection).
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Time-stamps should be seen in the image in Figure~\ref[meteor-reflection] (above and below the meteor reflection).
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Time-stamping should be improved in future by digitization of GPS signal received by the antenna on the observational station. Following that, the GPS signal can be directly sampled by a dedicated receiver and one separate ADC module. The datafile consists of samples from channels of radio-astronomy receivers along with the GPS signal containing the precise time information.
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Time-stamping should be improved in future by digitization of GPS signal received by the antenna on the observational station. Following that, the GPS signal can be directly sampled by a dedicated receiver and one separate ADC module. The datafile consists of samples from channels of radio-astronomy receivers along with the GPS signal containing the precise time information.
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100 [kHz]	&	–135	&	–121 \cr
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100 [kHz]	&	–135	&	–121 \cr
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1 [MHz]	&	–144	&	–134 \cr
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1 [MHz]	&	–144	&	–134 \cr
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10 [MHz]	&	–147	&	–146 \cr
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10 [MHz]	&	–147	&	–146 \cr
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100 [MHz]	&	n/a	&	–148 \cr
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100 [MHz]	&	n/a	&	–148 \cr
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}
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}
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\caption/t The phase noise of the used Silicon Laboratories Si570 chip. Offset frequency is measured from carrier frequency. Values shown in the table are given for two different carrier frequencies.
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\caption/t The phase noise of the used Silicon Laboratories Si570 chip. Offset frequency is measured from carrier frequency. Values shown in the table are given for two different carrier frequencies. Adopted from \cite[si570-chip].
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\endinsert
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\endinsert
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
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\label[signal-cables] \secc Signal cable connectors
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\label[signal-cables] \secc Signal cable connectors
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Several widely used and commercially easily accessible differential connectors were considered to be used in our design.
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Several widely used and commercially easily accessible differential connectors were considered to be used in our design:
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\begitems
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\begitems
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* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* HDMI, % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
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* SATA  		%{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* SATA,  		%{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]
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* DisplayPort 		%[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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* DisplayPort, or 		%[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>
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* SAS/miniSAS
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* SAS/miniSAS.
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\enditems
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\enditems
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Finally, MiniSAS connector was chosen as the best option to be used in connecting multiple ADC modules together. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable, which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It also has SPI configuration lines which can be seen in Figure~\ref[img-miniSAS-cable] as the standard pinheader connector.
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Finally, MiniSAS connector was chosen as the best option to be used in connecting multiple ADC modules together. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable, which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It also has SPI configuration lines which can be seen in Figure~\ref[img-miniSAS-cable] as the standard pinheader connector.
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The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. SMT design may eventually decrease the durability of the connector even if the outer metal housing of the connector is designed to be mounted using a standard through-hole mounting method.
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The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. SMT design may eventually decrease the durability of the connector even if the outer metal housing of the connector is designed to be mounted using a standard through-hole mounting method.
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\midinsert
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\midinsert
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\clabel[img-miniSAS-cable]{Used miniSAS cable}
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\clabel[img-miniSAS-cable]{Used miniSAS cable}
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\picw=5cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\picw=5cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\caption/f An example of miniSAS cable similar to used.
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\caption/f An example of a miniSAS cable.
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\endinsert
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\endinsert
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\secc Signal integrity requirements
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\secc Signal integrity requirements
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\label[diff-signaling]
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\label[diff-signaling]
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We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in a single line output mode, implying a 40 MHz output bit rate. This implies a $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5~m light path in a free space. If the copper PCB with FR4 substrate layer or the coaxial/twinax cable is used, we could obtain the velocity factor of 0.66 in the worst case. Consequently, the light path for the same bit rate $t_s$ will be 4.95~m. Although we do not have any cables in the system with comparable lengths, the worst data bit skew described by data sheets of the used components is $0.3 \cdot t_s$, which is 1.485~m. Therefore the length matching is not critical in our current design operating on the lowest sampling speed. The length matching may become critical in future versions with higher sampling rates, where the cable length must be matched. However SATA cabling technology is already prepared for that case and matched SATA cables are a standard merchandise.
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We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in a single line output mode, implying a 40 MHz output bit rate. This implies a $t_s=25$~ns time length of data bit, which is equivalent to 7.5~m light path in a free space. If the copper PCB with FR4 substrate layer or the coaxial/twinax cable is used, we could obtain the velocity factor of 0.66 in the worst case. Consequently, the light path for the same bit rate $t_s$ will be 4.95~m. Although we do not have any cables in the system with comparable lengths, the worst data bit skew described by data sheets of the used components is $0.3 \cdot t_s$, which is 1.485~m. Therefore the length matching is not critical in our current design operating on the used sampling speed. The length matching may become critical in future versions with higher sampling rates, where the cable length must be matched. However SATA cabling technology is already prepared for that case and matched SATA cables are a standard merchandise.
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\secc ADC modules design
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\secc ADC modules design
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\midinsert
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\clabel[adcdual-preview]{Preview of designed ADCdual PCB}
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\picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG
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\picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG
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\caption/f Realised PCB of ADCdual01A modules. Differential pairs routings are clearly visible.
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\endinsert
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\secc ADC selection
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There exist several standard ADC signalling formats currently used in communication with FPGA.
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There exist several standard ADC signalling formats currently used in communication with FPGA:
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\begitems
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\begitems
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  * DDR LVDS
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  * DDR LVDS,
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  * JEDEC 204B
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  * JEDEC 204B,
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  * JESD204A
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  * JESD204A,
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  * Paralel LVDS
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  * Paralel LVDS,
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  * Serdes
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  * Serdes,
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  * serial LVDS
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  * serial LVDS.
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\enditems
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\enditems
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As a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. A small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though. It is incapable of handling the differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analog single ended channels).
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As a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. A small number of differential pairs is an important parameter determining the construction complexity and reliability~\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though. It is incapable of handling the differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analog single ended channels).
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If we add a requirement of a separate output for every analog channel and a 16bit depth, we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in Table~\ref[ADC-types].
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If we add a requirement of a separate output for every analog channel and a 16bit depth, we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in Table~\ref[ADC-types].
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\midinsert
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\midinsert
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\typosize[9/11] \def\t
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\typosize[9/11] \def\t
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Package & \multispan7 \hfil 52-Lead (7mm $\times$ 8mm) QFN \hfil \strut \cr
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Package & \multispan7 \hfil 52-Lead (7mm $\times$ 8mm) QFN \hfil \strut \cr
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}
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}
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\caption/t The summary of the currently available ADC types and theirs characteristics.
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\caption/t The summary of the currently available ADC types and theirs characteristics.
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\endinsert
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\endinsert
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All parts in this category are compatible with one board layout. The main differences lay in the sampling frequency and in the signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However, all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated, etc.).  We have selected two slowest types for our evaluation design. Following that, a PCB for this part have been designed.
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All parts in this category are compatible with one board layout. The main differences lay in the sampling frequency and in the signal to noise ratio, with the slowest having a maximum sampling frequency of 20~MSPS. However, all of them have a minimal sampling frequency of 5~MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated, etc.).  For the first testing realisation, we have selected two slowest types for our evaluation design -- LTC2271 and LTC2190. Following that, a PCB for this part have been designed.
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We have decided that ADCdual01A modules will have a standard MLAB construction layout with four mounting holes in corners aligned in defined raster of 400 mils.
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We have decided that ADCdual01A modules will have a standard MLAB construction layout with four mounting holes in corners aligned in defined raster of 400 mils.
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Data serial data outputs of ADC modules should be connected directly by LVDS signalling levels conducted by SATA cables to FPGAs for the basic primary signal processing. The ADC chips used in the modules have a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel.  This creates a signal concept enabling a selection of the proper bus bit-width according to the sampling rate (the higher bus bit-width downgrades signalling speed and vice versa.)
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Data serial data outputs of ADC modules should be connected directly by LVDS signalling levels conducted by SATA cables to FPGAs for the basic primary signal processing. The ADC chips used in the modules have a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel.  This creates a signal concept enabling a selection of the proper bus bit-width according to the sampling rate (the higher bus bit-width downgrades signalling speed and vice versa.)
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In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used as described in Section~\ref[signal-cables].
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In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable is used as described in Section~\ref[signal-cables].
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KiCAD design suite had been chosen for PCB layout. However, the version, despite having integrated CERN Push \& Shove routing capability, is slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad,  the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
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As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
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KiCAD design suite had been chosen for PCB layout. As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to official KiCAD GitHub library repository. Thus, they are now publicly available.
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ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used.
162
ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used:
174
 
163
 
175
\begitems
164
\begitems
176
    * 1-lane mode
165
    * 1-lane mode,
177
    * 2-lane mode
166
    * 2-lane mode,
178
    * 4-lane mode
167
    * 4-lane mode.
179
\enditems
168
\enditems
180
 
169
 
181
All of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in 1-lane mode is shown in Figure~\ref[1-line-out].
170
All of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. The 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in the 1-lane mode is shown in Figure~\ref[1-line-out].
182
 
171
 
183
\midinsert
172
\midinsert
184
\clabel[1-line-out]{Single line ADC output signals}
173
\clabel[1-line-out]{Single line ADC output signals}
185
\picw=15cm \cinspic ./img/ADC_single_line_output.png
174
\picw=15cm \cinspic ./img/ADC_single_line_output.png
186
\caption/f Digital signalling schema for 1-line ADC digital output mode.
175
\caption/f Digital signalling schema for 1-line ADC digital output mode.
187
\endinsert
176
\endinsert
188
 
177
 
189
ADCdual01A parameters can be set either by jumper setup (referred to as a parallel programming  in the device's data sheet) or by SPI interface. SPI interface has been chosen for our system, because of the parallel programming's lack of options (test pattern output setup for example).
178
ADCdual01A parameters can be set either by jumper setup (referred to as a parallel programming  in the device's data sheet) or by SPI interface. SPI interface has been chosen for our system, because of the parallel programming's lack of options (test pattern output setup for example).
190
 
179
 
191
Complete schematic diagram of ADCdual01A module board is included in the appendix.
180
Figure~\ref[adcdual-preview] shows realized ADCdual01A module. Complete schematic diagram of ADCdual01A module board is included in Appendix~\ref[adc-scheme].
192
 
-
 
193
 
-
 
194
\secc ADC modules interface
-
 
195
 
181
 
196
\midinsert
182
\midinsert
-
 
183
\clabel[adcdual-preview]{Preview of designed ADCdual PCB}
197
\picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG
184
\picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG
198
\picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG
185
\picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG
199
\caption/f Realised PCB of FMC2DIFF01A module.
186
\caption/f Realised PCB of ADCdual01A module. Differential pairs routings are clearly visible.
200
\endinsert
187
\endinsert
201
 
188
 
-
 
189
 
-
 
190
 
-
 
191
\secc ADC modules interface
-
 
192
 
202
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in Figrue~\ref[VITA57-regions].
193
Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side. It is designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in Figure~\ref[VITA57-regions].
203
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the Appendix.
194
This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in Appendix~\ref[fmc-scheme].
204
 
195
 
205
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case with ML605 development board. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
196
The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case with ML605 development board. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).
206
Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
197
Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
207
 
198
 
208
LVPECL level signal connectors on FMC2DIFF01A board are dedicated to transmit the clock signals. We have selected  the SY55855V and SY55857L dual translators. Dual configuration in useful due to fact, that SATA cable contains two differential pairs.
199
LVPECL level signal connectors on FMC2DIFF01A board are dedicated to transmit the clock signals. We have selected  the SY55855V and SY55857L dual translators. Dual configuration in useful due to fact, that SATA cable contains two differential pairs.
Line 212... Line 203...
212
 
203
 
213
The SY55857L is a fully differential, a high-speed dual translator optimized for accepting any logic standard from the single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].
204
The SY55857L is a fully differential, a high-speed dual translator optimized for accepting any logic standard from the single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].
214
 
205
 
215
Inputs of both used chips are terminated accordingly to the used logic. The LVDS input is terminated differentially by 100~$\Omega$ resistor between the positive and the negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1.3 V) for direct termination by 50~$\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
206
Inputs of both used chips are terminated accordingly to the used logic. The LVDS input is terminated differentially by 100~$\Omega$ resistor between the positive and the negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1.3 V) for direct termination by 50~$\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
216
 
207
 
217
\midinsert
-
 
218
\clabel[ML605-development-board]{ML605 development board}
-
 
219
\picw=10cm \cinspic ./img/ML605-board.jpg
-
 
220
\caption/f FPGA ML605 development board.
-
 
221
\endinsert
-
 
222
 
208
 
223
\midinsert
209
\midinsert
224
\clabel[VITA57-regions]{VITA57 board geometry}
210
\clabel[VITA57-regions]{VITA57 board geometry}
225
\picw=10cm \cinspic ./img/VITA57_regions.png
211
\picw=10cm \cinspic ./img/VITA57_regions.png
226
\caption/f Definition of VITA57 regions.
212
\caption/f Definition of VITA57 regions.
Line 266... Line 252...
266
\caption/t SPI system interconnections.
252
\caption/t SPI system interconnections.
267
\endinsert
253
\endinsert
268
 
254
 
269
SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures.
255
SPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures.
270
 
256
 
-
 
257
Realized FMC2DIFF01A module is shown in Figure~\ref[FMC-realized].
271
 
258
 
272
\midinsert \clabel[clock-interconnections]{System clock interconnections}
259
\midinsert \clabel[clock-interconnections]{System clock interconnections}
273
\ctable {lccc}
260
\ctable {lccc}
274
{
261
{
275
Signal	&	FMC signal	&	FMC2DIFF01A	&	ADCdual01A	\cr
262
Signal	&	FMC signal	&	FMC2DIFF01A	&	ADCdual01A	\cr
Line 279... Line 266...
279
SDGPSDO01A LO	&	CLK0\_M2C	&	J3-1 (PECL IN)	&	N/A	\cr
266
SDGPSDO01A LO	&	CLK0\_M2C	&	J3-1 (PECL IN)	&	N/A	\cr
280
}
267
}
281
\caption/t Clock system interconnections.
268
\caption/t Clock system interconnections.
282
\endinsert
269
\endinsert
283
 
270
 
-
 
271
\midinsert
-
 
272
\clabel[FMC-realized]{Realized FMC2DIFF01A module}
-
 
273
\picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG
-
 
274
\picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG
-
 
275
\caption/f Realised PCB of FMC2DIFF01A module.
-
 
276
\endinsert
-
 
277
 
-
 
278
 
-
 
279
\secc FPGA data concentrator
-
 
280
 
-
 
281
 
284
\secc FPGA function
282
This section describes a specification of data concentrator built using FPGA board. The HDL implementation was created by my colleague Ond{\v r}ej Sychrovsk{\'y}. Detailed description of the currently implemented FPGA functions can be found in a separate paper~\cite[fpga-middleware].
-
 
283
 
-
 
284
\midinsert
-
 
285
\clabel[ML605-development-board]{ML605 development board}
-
 
286
\picw=10cm \cinspic ./img/ML605-board.jpg
-
 
287
\caption/f FPGA ML605 development board.
-
 
288
\endinsert
285
 
289
 
286
Several tasks in the separate FPGA blocks are performed by FPGA. In the first block, the FPGA prepares a sampling clock for ADCdual01A modules by dividing the signal from the main local oscillator. This task represents a separate block in FPGA and runs asynchronously to other logical circuits. The second block is a SPI configuration module, which sends configuration words to ADC modules and it is activated by opening of Xillybus interface file. The third block represents the main module, which resolves ADC - PC communication itself and it communicates via PCIe, collect data from ADC hardware and creates data packet, Table~\ref[xillybus-interface]. The last block is activated after the ADC is configurated via SPI.
290
Several tasks in the separate IP blocks are performed by FPGA. In the first block, the FPGA prepares a sampling clock for ADCdual01A modules by dividing the signal from the main local oscillator. This task represents a separate block in FPGA and runs asynchronously to other logical circuits. The second block is a SPI configuration module, which sends configuration words to ADC modules and it is activated by opening of Xillybus interface file. The third block represents the main module, which resolves ADC -- PC communication itself and it communicates via PCIe, collect data from ADC hardware and creates data packet, Table~\ref[xillybus-interface]. The last block is activated after the ADC is configurated via SPI.
287
 
291
 
288
The communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in a system device file named  "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are shown in Table~\ref[xillybus-interface].
292
The communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in a system device file named  "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are shown in Table~\ref[xillybus-interface].
289
 
293
 
290
\midinsert
294
\midinsert
291
\def\tabiteml{ }\let\tabitemr=\tabiteml
295
\def\tabiteml{ }\let\tabitemr=\tabiteml
Line 301... Line 305...
301
 
305
 
302
The data packet block which is carried on PCI Express is described in Table~\ref[xillybus-interface]. The data packet consist of several 32bit words. The first word contains FRAME number and it is filled with saw signal for now, with incremental step taking place every data packet transmission. The following data words contain samples from ADCs' first and second channel. Samples from every channel are transmitted in pairs of two samples. Number of ADC channels is expandable according to the number of physically connected channels. An CRC word may possibly be added in the future to the end of the transmission packet for data integrity validation.
306
The data packet block which is carried on PCI Express is described in Table~\ref[xillybus-interface]. The data packet consist of several 32bit words. The first word contains FRAME number and it is filled with saw signal for now, with incremental step taking place every data packet transmission. The following data words contain samples from ADCs' first and second channel. Samples from every channel are transmitted in pairs of two samples. Number of ADC channels is expandable according to the number of physically connected channels. An CRC word may possibly be added in the future to the end of the transmission packet for data integrity validation.
303
 
307
 
304
FRAME word at the beginning of data packet, now filled with incrementing and overflowing saw signal, is used to ensure that no data samples ale lost during the data transfers from FPGA. FRAME signal may be used in the future for pairing the ADC samples data packet with another data packet. This new additional data packet should carry meta-data information about the sample time jitter, current accuracy of the local oscillator frequency etc.
308
FRAME word at the beginning of data packet, now filled with incrementing and overflowing saw signal, is used to ensure that no data samples ale lost during the data transfers from FPGA. FRAME signal may be used in the future for pairing the ADC samples data packet with another data packet. This new additional data packet should carry meta-data information about the sample time jitter, current accuracy of the local oscillator frequency etc.
305
 
309
 
306
Detailed description of the currently implemented FPGA functions can be found in a separate paper~\cite[fpga-middleware]. HDL source codes for FPGA at a state in which it was used are included on the enclosed CD. More recent development versions are publicly available from MLAB sources repository.
-
 
307
Detailed description of currently implemented FPGA functions can be found in separate paper~\cite[fpga-middleware]. HDL\glos{HDL}{Hardware description language} source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository~\cite[mlab-sdrx].
310
HDL source codes for FPGA at a state in which it was used are included on the enclosed CD. Future development versions will be publicly available from MLAB sources repository~\cite[mlab-sdrx].
308
 
311
 
309
\secc Data reading and recording
312
\secc Data reading and recording
310
 
313
 
311
In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool has been used to create a basic RAW data grabber to record and interactively view waterfall plots using the data streams output from ADC modules.
314
In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool has been used to create a basic RAW data grabber to record and interactively view waterfall plots using the data streams output from ADC modules. The ADC recorder flow graph is shown in Figure~\ref[grabber-flow-graph].
312
 
315
 
313
\midinsert
316
\midinsert
314
\clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing}
317
\clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing}
315
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/screenshots/Grabber.grc.png }
318
\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/screenshots/Grabber.grc.png }
316
\par\nobreak \vskip\wd0 \vskip-\ht0
319
\par\nobreak \vskip\wd0 \vskip-\ht0
317
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
320
\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
318
\caption/f The ADC recorder flow graph created in gnuradio-companion.
321
\caption/f The ADC recorder flow graph created in gnuradio-companion.
319
\endinsert
322
\endinsert
320
 
323
 
321
\midinsert
324
\midinsert
-
 
325
\clabel[grabber-data]{User interface window of a running ADC grabber}
322
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
326
\picw=15cm \cinspic ./img/screenshots/Grabber_running.png
323
\caption/f User interface window of a running ADC grabber.
327
\caption/f User interface window of a running ADC grabber.
324
\endinsert
328
\endinsert
325
 
329
 
326
The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. The signal is grabbed to the file with the exactly same format as described in Table \ref[xillybus-interface].
330
The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. The signal is grabbed to the file with the exactly same format as described in Table \ref[xillybus-interface]. An example of interactive grabber-viewer showing a part of the grabbed signal is in Figure~\ref[grabber-data].
327
 
331
 
328
 
332
 
329
 
333