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\secc Differential signalling
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\secc Differential signalling
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This concept of scalable design requires relatively long traces between ADC and digital unit which captures the data and performs computations. Distance of digital processing unit and analog to digital conversion unit has advantage in noise retention typically produced by digital circuits. Those digital circuits such as FPGA or other flip-flops block and traces usually works on high frequencies and emits wideband noise with relatively low power. In such case any distance increase between noise source and analog signal source increase S/N significantly. But this distance also brings problems with digital signal transmission between ADC and computational unit. But this obstruction should be resolved easier in free space than on board routing. The high quality differential signalling shielded cables should be used. This technology have two advantages on PCB signal routing. It can use two wire twisting for leak inductance suppression of signal path. And this twisted pair may be additionally shielded by uninterrupted metal foil.
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This concept of scalable design requires relatively long traces between ADC and digital unit which captures the data and performs computations. Distance of digital processing unit and analog to digital conversion unit has advantage in noise retention typically produced by digital circuits. Those digital circuits such as FPGA or other flip-flops block and traces usually works on high frequencies and emits wideband noise with relatively low power. In such case any distance increase between noise source and analog signal source increase S/N significantly. But this distance also brings problems with digital signal transmission between ADC and computational unit. But this obstruction should be resolved easier in free space than on board routing. The high quality differential signalling shielded cables should be used. This technology have two advantages on PCB signal routing. It can use two wire twisting for leak inductance suppression of signal path. And this twisted pair may be additionally shielded by uninterrupted metal foil.
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\secc Phase matching
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For multiple antenna radioastronomy project, system phase stability is mandatory. It allows precise high resolution imaging of object.
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High phase stability in this scalable design is achieved by centralised frequency generation and distribution with multi-output LVPECL hubs. These hubs have equiphased outputs for multiple devices.
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This design ensures that all devices have access to defined phase and known frequency.
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\sec System description
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\sec System description
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In this section testing system will be described.
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In this section testing system will be described.
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\secc Frequency synthesis
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\secc Frequency synthesis
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Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it. This central oscillator has software defined GPS disciplined control loop for frequency stabilisation. This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.
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Centralised topology was used for frequency synthesis. One precise high frequency and low jitter digital oscillator was used and other working frequencies are delivered by division from it. This central oscillator has software defined GPS disciplined control loop for frequency stabilisation.\ref{gpsdo} This method was used in order to meet modern requirements on radioastronomy equipment, which needs precise frequency and phase stability on wide area for effective radioastronomy imaging.
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\fnote{This design was developed in parallel to this diploma thesis construction as related project, but it is not explicitly required by specification.}
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\secc Signal connectors
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\secc Signal connectors
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Several widely used and commercially easily accessible differential connectors was considered.
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Several widely used and commercially easily accessible differential connectors was considered.
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New PCB footprints must be designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. They are now publicly accessible from official KiCAD repository at GitHub.
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New PCB footprints must be designed for FMC, SATA a and miniSAS connectors. These new footprints were committed to KiCAD github library repository. They are now publicly accessible from official KiCAD repository at GitHub.
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\secc ADC modules interface
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\secc ADC modules interface
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All two ADCdual01A modules was connected to FPGA ML605 board trough
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All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3.
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This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix.
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\midinsert
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\midinsert
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\picw=10cm \cinspic ./img/ML605-board.jpg
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\picw=10cm \cinspic ./img/ML605-board.jpg
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\caption/f Used FPGA ML605 development board.
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\caption/f Used FPGA ML605 development board.
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\endinsert
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\endinsert
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Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows connection of any number of ADC modules in range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors. Other supporting signal should be routed directly to SATA connectors on adapter.
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Signal configuration used in testing construction is described in tables.
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\secc Output data format
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\secc Output data format
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\midinsert
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\midinsert
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\ctable {cccccccccc}{
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\ctable {cccccccccc}{
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\hfil
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\hfil
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