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\chap Trial design
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\chap Trial design
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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalisation of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System.
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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalization of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System.
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\sec Required parameters
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\sec Required parameters
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Wide dynamical range and high IP3 are desired. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise.
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Wide dynamical range and high IP3 are desired. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise.
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.).
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.).
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.
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\secc Differential signalling
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\secc Differential signaling
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The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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The concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA or other flip-flops block and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time a long distance brings problems with the digital signal transmission between ADC and computational unit. This obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used. This technology has two advantages over PCB signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.
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\secc Phase matching
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\secc Phase matching
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For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows precise high resolution imaging of objects.
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For multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows precise high resolution imaging of objects.
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High phase stability in our scalable design is achieved through centralised frequency generation  and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices.
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High phase stability in our scalable design is achieved through centralized frequency generation  and distribution with multi-output LVPECL hubs, that have equiphased outputs for multiple devices.
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This design ensures that all devices have access to the defined phase and known frequency.
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This design ensures that all devices have access to the defined phase and known frequency.
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\sec System description
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\sec System description
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In this section testing system will be described.
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In this section testing system will be described.
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\secc Frequency synthesis
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\secc Frequency synthesis
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We have used a centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used, while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used, while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilization.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging.
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose.
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator.  This signal should use high quality differential signaling cable -- we should use SATA cable for this purpose.
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram.
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram.
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Time-marking should be improved in future by digitalisation GPS signal directly with dedicated ADC channel.  Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information.
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Time-marking should be improved in future by digitalisation GPS signal directly with dedicated ADC channel.  Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information.
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\picw=10cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\picw=10cm \cinspic ./img/miniSAS_SATA_cable.jpg
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\caption/f A type of miniSAS cable similar to used.
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\caption/f A type of miniSAS cable similar to used.
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\endinsert
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\endinsert
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\secc Signal integrity requirements
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\secc Signal integrity requirements
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\label[diff-signaling]
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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate.
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We use ADC modules that have DATA clock frequency eight times higher than sampling frequency in single line output mode, implying a 40 MHz output bit rate. This imply $ 1/4*10^7 = 25$ ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate will be 4.95 m. Although we do not have any cables in system with comparable lengths, worst data bit skew described by data sheets of used components is $0.3*sample time$ time which is 1.485 m. Therefore length matching is not critical in our design.
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\secc ADC modules design
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\secc ADC modules design
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The ADC modules have a standard MLAB construction scheme with four mounting holes in corners aligned in defined raster.
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Data serial data outputs of ADC modules should be connected directly to FPGAs for the basic primary signal processing. The ADC chip used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel.  This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)
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In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used.
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A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad,  the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
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As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
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\secc ADC selection
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\secc ADC selection
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There exist several ADC signalling formats currently used in communication with FPGA.
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There exist several ADC signaling formats currently used in communication with FPGA.
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\begitems
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\begitems
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  * DDR LVDS
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  * DDR LVDS
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  * JEDEC 204B
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  * JEDEC 204B
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  * JESD204A
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  * JESD204A
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Because it uses the smallest number of differential pairs, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}
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Because it uses the smallest number of differential pairs, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}
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An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels).
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An ultrasound AFE chip seems to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC). Because this IO has many ADC channels the scaling is possible only by a factor of 4 receivers (making 8 analogue channels).
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If we require a separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements.  We have summarised the ADCs in the following table \ref[ADC-type]
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If we require a separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these requirements.  We have summarized the ADCs in the following table \ref[ADC-type]
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\midinsert \clabel[ADC-types]{Available ADC types}
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\midinsert \clabel[ADC-types]{Available ADC types}
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\ctable{lrrrrrcc}{
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\ctable{lrrrrrcc}{
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\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
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SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
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\caption/t The summary of available ADC types and theirs characteristics.
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\caption/t The summary of available ADC types and theirs characteristics.
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\endinsert
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\endinsert
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All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
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All parts in this category are compatible with one board layout. Main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
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The ADC modules have a standard MLAB construction scheme with four mounting holes in corners aligned in defined raster.
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Data serial data outputs of ADC modules should be connected directly to FPGAs for the basic primary signal processing. The ADC chip used in the modules has a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel.  This creates a signal concept enabling a selection of a proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)
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In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used.
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A KiCAD design suite had been chosen for PCB layout. However, the version is, despite having integrated CERN Push \& Shove routing capability, slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad,  the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.
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As a part of work on the thesis, new PCB footprints for FMC, SATA a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.
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ADCdual01A module has several digital data output formats
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\begitems
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    * 1-lane mode
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\enditems
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All of these modes are supported by module design. For discused data acquisition system the 1-lane mode was selected. 1-lane mode allows minimal number of differential pairs between ADCdual01A and FPGA. Digital signaling scheme used in 1-lane mode is shown in image \ref[1-line-out].
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\midinsert
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\clabel[1-line-out]{Single line ADC output signals}
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\picw=15cm \cinspic ./img/ADC_single_line_output.png
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\caption/f Digital signaling shema for  1-line  ADC digital output mode.
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\endinsert
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ADCdual01A parameters can be set either by jumper setup (refered as parallel programming  in device's data sheet) or by SPI interface. SPI interface has been selected for our system, because parallel programming lacks of options (test pattern output setup for example).
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Complete schematic diagram of ADCdual01A module board is included in the appendix.
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\secc ADC modules interface
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\secc ADC modules interface
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Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
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Both of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter module expects the presence of FMC LPC connector and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].
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This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of this adapter board is included in the appendix.
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This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.
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The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realised without the use of massive RFI mitigation techniques).
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The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case. (In PC box analog circuits cannot be realised without the use of massive RFI mitigation techniques).
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Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
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Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.
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\midinsert
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\midinsert
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\caption/f Definition of VITA57 regions.
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\caption/f Definition of VITA57 regions.
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\endinsert
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\endinsert
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Several SATA connectors and two miniSAS connectors are populated on this board.  This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
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Several SATA connectors and two miniSAS connectors are populated on this board.  This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
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Differential pairs routed on PCB are not matched for lenghts. Althought inter differential pairs
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Lengths of differential pairs routed on PCB of module are not matched between pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless signals within differential pairs itself are matched for length. Internal signal traces length mating of differential pairs is mandatory in order to avoid dynamic logic hazard conditions on digital signals. Thus clocks signals are routed most precisely on all designed boards.
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Signal configuration used in our trial design is described in the following tables.
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Signal configuration used in our trial design is described in the following tables.
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\secc Output data format
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\secc Output data format
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Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal.
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Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal.
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\secc ADC module parameters
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\secc ADC module parameters
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Two pieces of ADC modules were completed and tested. The first piece, labeled ADC1, has LTC21190
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Two pieces of ADC modules were completed and tested. The first piece, labeled ADC1, has LTC2190
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ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula
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ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
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\caption/f Sine signal sampled by ADC1 module with LTC21190 and LT6600-5 devices.
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\endinsert
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ADC1 CH1  maximal input 705.7 mV
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\label[ADC1-gain]
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$$
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$$
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A = {1580 \times R_1 \over R_1 + R_2}
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A = {806 \times R_1 \over R_1 + R_2}
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$$
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$$
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Where is
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Where is
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\begitems
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\begitems
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  * $A$ -  Gain of input aplifier.
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  * $A$ -  Gain of input amplifier.
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  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
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  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
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  * $R_2$ - Value of serial resitors at operational apmlifier inputs.
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  * $R_2$ - Value of serial resistors at operational amplifier inputs.
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\enditems
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\enditems
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We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply $A = 0.815$. That value of A is confirmed by measurement.
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In our measurement setup we have H1012 Ethernet transformer connected at inputs of ADC. Transformer has 10\% tolerance in impedance and amplification. We measured ADC saturation voltage 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated transformer gain.
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\midinsert
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\midinsert
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\clabel[ADC1-FFT]{ADC1 sine test FFT}
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\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png
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\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
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\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
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\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.
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\endinsert
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\endinsert
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1k
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ADC2 CH1 maximal input 380 mV
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For ADC2 we must use formula with different constant \ref[ADC1-gain]. ADC2 module has LT6600-2.5 populated and gain is $A = 2.457$ with same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.
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\label[ADC2-gain]
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$$
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$$
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A = {806 \times R_1 \over R_1 + R_2}
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A = {1580 \times R_1 \over R_1 + R_2}
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$$
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$$
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Where is
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Where is
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\begitems
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\begitems
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  * $A$ -  Gain of input aplifier.
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  * $A$ -  Gain of input amplifier.
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  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
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  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
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  * $R_2$ - Value of serial resitors at operational apmlifier inputs.
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  * $R_2$ - Value of serial resistors at operational amplifier inputs.
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\enditems
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Both images confirms that ADC modules have input dynamical range 80 dB at least.
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ADCdual01A module has several digital data output formats
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\begitems
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    * 1-lane mode
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\enditems
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\enditems
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\midinsert
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\clabel[ADC2-FFT]{ADC2 sine test FFT}
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\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png
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All of these modes are supported by module design. For discused data aquisition system the 1-lane mode was selected. 1-lane mode allows minimal number of diff pais between ADCdual01A and FPGA.
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\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
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\endinsert
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ADCdual01A parameters can be set either by jupmper setup (refered as parallel pragramming  in device's datasheet) or by SPI interface. SPI interface has been selected for our system, because papralel programming lacks of option of test pattern output setup.
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Computed FFT spectra for measured signal are shown in images \ref[ADC2-FFT] and \ref[ADC1-FFT].  Both images confirms that ADCdual01A modules have input dynamical range 80 dB at least.
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\chap Example of usage
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\chap Example of usage
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%\sec Simple polarimeter station
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For additional validation of system design a receiver setup was constructed.
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\sec Basic interferometer station
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\sec Basic interferometer station
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For system evaluation basic interferometry station was constructed.
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Interferometry station was selected as most basic setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematic of used setup is shown in image \ref[block-schematic]. Two ground-plane antennas were used and mounted outside of balcony at CTU building at location 50°4'36.102"N, 14°25'4.170"E. Antennas were equipped  by LNA01A amplifiers. Coaxial cable length are matched for 5 meters. And antennas were isolated by common mode ferrite bead mounted on cable for minimize signal coupling between antennas. Evaluation system consists SDGPSDO local oscillator subsystem used for tunning local oscillator frequency.
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\midinsert
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\clabel[block-schematic]{Receiver block schematic}
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\picw=10cm \cinspic ./img/Coherent_UHF_SDR_receiver.png
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\caption/f Complete receiver block schematic of dual antenna interferometric station.
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\endinsert
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\midinsert
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\clabel[meteor-reflection]{Meteor reflection}
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\clabel[meteor-reflection]{Meteor reflection}
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\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
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\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
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\caption/f Meteor reflection received by evaluation setup.
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\caption/f Meteor reflection received by evaluation setup.
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\picw=10cm \cinspic ./img/screenshots/phase_difference.png
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\picw=10cm \cinspic ./img/screenshots/phase_difference.png
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\caption/f Demonstration of phase difference between antennas.
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\caption/f Demonstration of phase difference between antennas.
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\midinsert
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\clabel[block-schematic]{Receiver block schematic}
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\picw=10cm \cinspic ./img/Coherent_UHF_SDR_receiver.png
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\caption/f Complete receiver block schematic of dual antenna interferometric station.
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\endinsert
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%\sec Simple passive Doppler radar
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%\sec Simple passive Doppler radar
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%\sec Simple polarimeter station
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\chap Proposed final system
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\chap Proposed final system
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Construction of a final system which is supposed to be employed for real radioastronomy observations will be described. This chapter is mainly a theoretical analysis of data handling systems. Realisation of these ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
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Construction of a final system which is supposed to be employed for real radioastronomy observations will be described. This chapter is mainly a theoretical analysis of data handling systems. Realization of these ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.
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\sec Custom design of FPGA board
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\sec Custom design of FPGA board
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In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of this board to another adapter board with PCIe we expect a use of a host interface.
307 
In the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than trial design. It should be compatible with MLAB which is further backward compatible with the existing or improved design of ADC modules. For a connection of this board to another adapter board with PCIe we expect a use of a host interface.
293 
Thunderbolt technology standard was expected to be used in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution.
308 
Thunderbolt technology standard was expected to be used in this PC to PCIe -> FPGA module. Thunderbolt chips are currently available on the market for reasonable prices. However, a problem lies in the accessibility to their specifications, as they are only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution.