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\clabel[VITA57-regions]{VITA57 board geometry}
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\clabel[VITA57-regions]{VITA57 board geometry}
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\picw=10cm \cinspic ./img/VITA57_regions.png
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\picw=10cm \cinspic ./img/VITA57_regions.png
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\caption/f Definition of VITA57 regions.
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\caption/f Definition of VITA57 regions.
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\endinsert
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\endinsert
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% doplnit presny pocet konektoru
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Several SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
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Three differential logic input/output, one PECL input and one PECL output SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.
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Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals, that represents the worst scenario. Thus the clocks' signals are routed in the most precise way on all designed boards.
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Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals, that represents the worst scenario. Thus the clocks' signals are routed in the most precise way on all designed boards.
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Signal configuration used in our trial design is described in the following tables \ref[minisas-interface], \ref[SPI-system] and \ref[clock-interconnections].
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Signal configuration used in our trial design is described in the following tables \ref[minisas-interface], \ref[SPI-system] and \ref[clock-interconnections].
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Data packet block which is carried on PCI Express isa described in the table \ref[xillybus-interface]. The data packet consist of several 32bit words. The first word contains FRAME number and it is filled with saw signal for now, with incremental step taking place every data packet transmission. The following data words contain samples from ADCs' first and second channel. Samples from every channel are transmitted in pairs of two samples. Number of ADC channels is expandable according to the number of physically connected channels. An CRC word may possibly be added in the future to the end of the transmission packet for data integrity validation.
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Data packet block which is carried on PCI Express isa described in the table \ref[xillybus-interface]. The data packet consist of several 32bit words. The first word contains FRAME number and it is filled with saw signal for now, with incremental step taking place every data packet transmission. The following data words contain samples from ADCs' first and second channel. Samples from every channel are transmitted in pairs of two samples. Number of ADC channels is expandable according to the number of physically connected channels. An CRC word may possibly be added in the future to the end of the transmission packet for data integrity validation.
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FRAME word at the beginning of data packet, now filled with incrementing and overflowing saw signal, is used to ensure that no data samples ale lost during the data transfers from FPGA. FRAME signal may be used in the future for pairing the ADC samples' data packet with another data packet. This new additional data packet should carry meta-data information about the sample time jitter, current accuracy of the local oscillator frequency etc.
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FRAME word at the beginning of data packet, now filled with incrementing and overflowing saw signal, is used to ensure that no data samples ale lost during the data transfers from FPGA. FRAME signal may be used in the future for pairing the ADC samples' data packet with another data packet. This new additional data packet should carry meta-data information about the sample time jitter, current accuracy of the local oscillator frequency etc.
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Detailed description of the currently implemented FPGA functions can be found in a separate paper \cite[fpga-middleware]. HDL source codes for FPGA at a state in which it was used are included on the enclosed CD. More recent development versions are publicly available from MLAB sources repository.
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Detailed description of the currently implemented FPGA functions can be found in a separate paper \cite[fpga-middleware]. HDL source codes for FPGA at a state in which it was used are included on the enclosed CD. More recent development versions are publicly available from MLAB sources repository.
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Detailed description of currently implemented FPGA functions can be found in separate paper \cite[fpga-middleware]. HDL \glos{HDL}{Hardware description language} source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository \cite[mlab-sdrx].
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% doplnit odkaz na mlab repozitar
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\secc Data reading and recording
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\secc Data reading and recording
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In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool has been used to create a basic RAW data grabber to record and interactively view waterfall plots using the data streams output from ADC modules.
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In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool has been used to create a basic RAW data grabber to record and interactively view waterfall plots using the data streams output from ADC modules.
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