Subversion Repositories svnkaklik

Rev

Rev 1142 | Rev 1149 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log

Rev 1142 Rev 1145
Line 88... Line 88...
88 
\endinsert
 88 
\endinsert
89 
 
 89 
 
90 
Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
 90 
Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.
91 
 
 91 
 
92 
 
 92 
 
93 
\secc Signal cable connectors
 93 
\label[signal-cables] \secc Signal cable connectors
- 
 
 94 
 
94 
 
 95 
 
95 
\label[signal-cables]
 - 
 
96 
 
 96 
 
97 
Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
 97 
Several widely used and commercially easily accessible differential connectors were considered to be use in our design.
98 
 
 98 
 
99 
\begitems
 99 
\begitems
100 
* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>
 100 
* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>