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\medskip
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\medskip
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\noindent
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\noindent
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The summary of other additional required parameters:
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The summary of other additional required parameters:
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%
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%
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\begitems
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\begitems
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* Dynamic range better than 80 dB, see section \ref[dynamic-range-theory] for the explanation.
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* Dynamic range better than 80 dB, see Section \ref[dynamic-range-theory] for the explanation.
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* Phase stability between channels.
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* Phase stability between channels.
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* Low noise (all types).
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* Low noise (all types).
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* Sampling jitter better than 100 metres.
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* Sampling jitter better than 100 metres.
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* Support for any number of receivers in the range of 1 to 8.
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* Support for any number of receivers in the range of 1 to 8.
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\enditems
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\enditems
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This design ensures that all system devices have access to the defined phase and the known frequency.
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This design ensures that all system devices have access to the defined phase and the known frequency.
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\sec System description
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\sec System description
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This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed. Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consist antennas equipped by
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This section deals with the description of the trial version based on Xilinx ML605 development board, see Figure~\ref[ML605-development-board], available at the workplace. This FPGA parameters are more than sufficient of what we need for the fast data acquisition system being developed. Expected system configuration is shown in Figure~\ref[expected-block-schematic]. The system consist antennas equipped by
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%% dopsat celkovy popis systemu.
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%% dopsat celkovy popis systemu.
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\midinsert
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\midinsert
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\clabel[expected-block-schematic]{Expected system block schematic}
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\clabel[expected-block-schematic]{Expected system block schematic}
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As a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. A small number of differential pairs is an important parameter determining the construction complexity and reliability~\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though. It is incapable of handling the differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analog single ended channels).
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As a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. A small number of differential pairs is an important parameter determining the construction complexity and reliability~\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though. It is incapable of handling the differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analog single ended channels).
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If we add a requirement of a separate output for every analog channel and a 16bit depth, we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in Table~\ref[ADC-types].
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If we add a requirement of a separate output for every analog channel and a 16bit depth, we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in Table~\ref[ADC-types].
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\midinsert
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\midinsert
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\typosize[9/11] \def\t
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- |
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abiteml{ }\let\tabitemr=\tabiteml
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\typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml
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\clabel[ADC-types]{Available ADC types}
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\clabel[ADC-types]{Available ADC types}
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\ctable{lccccccc}{
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\ctable{lccccccc}{
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\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \cr
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SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
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SNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \cr
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| 148 |
SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr
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SFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \cr
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The SY55855V is a fully differential, CML/PECL/LVPECL-to-LVDS translator. It achieves LVDS signalling up to 1.5Gbps, depending on the distance and the characteristics of the media and noise coupling sources.
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The SY55855V is a fully differential, CML/PECL/LVPECL-to-LVDS translator. It achieves LVDS signalling up to 1.5Gbps, depending on the distance and the characteristics of the media and noise coupling sources.
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LVDS is intended to drive 50 $\Omega$ impedance transmission line media such as PCB traces, backplanes, or cables. SY55855V inputs can be terminated with a single resistor between the true and the complement pins of a given input \cite[SY55855V-chip].
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LVDS is intended to drive 50 $\Omega$ impedance transmission line media such as PCB traces, backplanes, or cables. SY55855V inputs can be terminated with a single resistor between the true and the complement pins of a given input \cite[SY55855V-chip].
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The SY55857L is a fully differential, a high-speed dual translator optimized for accepting any logic standard from the single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].
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The SY55857L is a fully differential, a high-speed dual translator optimized for accepting any logic standard from the single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].
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Inputs of both used chips are terminated accordingly to the used logic. The LVDS input is terminated differentially by 100~$\Omega$ resistor between the positive and the negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1.3 V) for direct termination by 50~$\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
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Inputs of both used chips are terminated accordingly to the used logic. The LVDS input is terminated differentially by 100~$\Omega$ resistor between the positive and the negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1.3~V) for the direct termination by 50~$\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.
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\midinsert
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\midinsert
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\clabel[VITA57-regions]{VITA57 board geometry}
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213 |
\clabel[VITA57-regions]{VITA57 board geometry}
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| 215 |
\picw=10cm \cinspic ./img/VITA57_regions.png
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214 |
\picw=10cm \cinspic ./img/VITA57_regions.png
|