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 Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1 MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.
 We calculate minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5MSPS as $8 * 2 * 5e6 = 80$ MB/s. Such data rate is at the limit of real writing speed o classical HDD and it is almost double of real bandwidth of USB 2.0 interface.
 \sec System scalability
 For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires.
 Interactive grabber viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal.
 \secc ADC module parameters
 Two pieces of ADC modules were completed and tested. The first piece, labeled ADC1, has LTC21190
-ADC chip populated with LT660015 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula
+ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which gives it an ability of an internal attenuation of input signal. The value of this attenuation $A$ is described by the following formula
-$$
-A = {1580 \times R_1 \over R_1 + R_2}
-$$
 \midinsert
 \picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
-\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.
+\caption/f Sine signal sampled by ADC1 module with LTC21190 and LT6600-5 devices.
 \endinsert
 ADC1 CH1  maximal input 705.7 mV
+$$
+A = {1580 \times R_1 \over R_1 + R_2}
+$$
+Where is
+\begitems
+  * $A$ -  Gain of input aplifier.
+  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
+  * $R_2$ - Value of serial resitors at operational apmlifier inputs.
+\enditems
 \midinsert
-\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
+\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png
-\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.
+\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
 \endinsert
-LTC2271
-6600125
 k
 ADC2 CH1 maximal input 380 mV
 $$
-D.R. = N * b *
+A = {806 \times R_1 \over R_1 + R_2}
 $$
 Where is
 \begitems
-  * N - number of receivers
+  * $A$ -  Gain of input aplifier.
-  * Mi
+  * $R_1$ - Output impedance of signal source (usually 50 Ohm).
+  * $R_2$ - Value of serial resitors at operational apmlifier inputs.
 \enditems
+Both images confirms that ADC modules have input dynamical range 80 dB at least.
 \chap Example of usage
 %\sec Simple polarimeter station

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