WebSVN – svnkaklik – Diff – /dokumenty/skolni/diplomka/description.tex

 Several tasks in separate FPGA blocks are performed by FPGA. In first block FPGA prepares sampling clock for ADCdual01A modules by division of main local oscillator. This task is separate block in FPGA and runs asynchronously to other logical circuits. Second block is SPI configuration module, which sends configuration words to ADC modules it is activated by opening of Xillybus interface file. Third block represents the main module, which resolves ADC - PC communication itself it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after ADC configuration via SPI.
 Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named  "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface].
 \midinsert
-\typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml
+\def\tabiteml{ }\let\tabitemr=\tabiteml
 \clabel[xillybus-interface]{Grabber binary output format}
 \ctable {lccccccccc}{
-\hfil & \multispan9 \hfil 160bit packet \hfil \crl \tskip4pt
+\hfil & \multispan9 \hfil 160bit packet \hfil \strut \crl \tskip4pt
-Data name &  FRAME  & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2  \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil  \cr
+Data name &  FRAME  & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2  \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \strut  \cr
 Data type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \cr
 Content & saw signal & $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ &  $t1$ &  $t_{1+1}$ \cr
+}
 \caption/t System device "/dev/xillybus_data2_r" data format
 \endinsert
 \secc Data reading and recording
 In order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view waterfall plots the data streams output from ADC modules.
 \midinsert
+\clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing}
-\picw=15cm \cinspic ./img/screenshots/Grabber.grc.png
+\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/screenshots/Grabber.grc.png }
+\par\nobreak \vskip\wd0 \vskip-\ht0
+\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
-\caption/f An ADC recorder flow graph created in gnuradio-companion.
+\caption/f The ADC recorder flow graph created in gnuradio-companion.
 \endinsert
 \midinsert
 \picw=15cm \cinspic ./img/screenshots/Grabber_running.png
 \caption/f User interface window of a running ADC grabber.
 The interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as it is described in table \ref[xillybus-interface].
 \sec Achieved parameters
+Trial design construction was tested for proper handling of sampling rates in range of 5 MSPS to 15 MSPS it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system.  Data recording of input signal is impossible above sampling rates around 7 MSPS due to bottleneck at HDD speed limits, it should be resolved by use of SSD disk drive. But it is not tested in our setup.
 \secc ADC module parameters
 Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]
 \label[ADC1-gain]
 $$
 A = {806 \cdot R_1 \over R_1 + R_2} \eqmark
 $$
   * $R_1$ - Output impedance of signal source (usually 50 Ohm).
   * $R_2$ - Value of serial resistors at operational amplifier inputs.
 \enditems
 We have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A is further confirmed by the measurement.
-In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. The transformer has a 10\% tolerance in impedance and amplification. We measured ADC saturation voltage of 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated transformer gain.
+In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of used transformer circuit is shown in picture   and circuit realization in photograph \ref[SMA2SATA-nest].
+% doplnit schema zapojeni transformatoru.
+Used signal generator Agilent 33220A has not optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. Although, we measured ADC saturation voltage of 705.7 mV (generator output) in this setup due to impedance mismatch and uncalibrated measurement setup and 1V ADC range selected by sense pin. This is relatively high error, but main result from this measurement is FFT plot shown in image \ref[ADC1-FFT], which confirms $>$80 dB dynamic range at ADC module input.
 \midinsert
 \clabel[ADC1-FFT]{ADC1 sine test FFT}
 \picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
 \caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.
 \endinsert
-For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.
+Similar test we performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances  of used setup.
 \label[ADC2-gain]
 $$
 A = {1580 \cdot R_1 \over R_1 + R_2} \eqmark
 $$
 \caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.
 \endinsert
 Computed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT].  Both images confirm that ADCdual01A modules have input dynamical range of 80 dB at least.
+\midinsert
+\clabel[SMA2SATA-nest]{Used balun transformer}
+\picw=15cm \cinspic ./img/SMA2SATA_nest1.JPG
+\caption/f Balun transformer circuit used for ADC parameters measurement. It is constructed from H1012 transformer salvaged from an old Ethernet card.
+\endinsert
 \chap Example of usage
 For additional validation of system characteristics a receiver setup has been constructed.
 \sec Basic interferometric station
 Interferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N,  14$^\circ$ 25' 4.170'' E.
 Antennae were equipped  by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency.
 \midinsert
 \clabel[block-schematic]{Receiver block schematic}
-\picw=10cm \cinspic ./img/Coherent_UHF_SDR_receiver.png
+\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }
+\par\nobreak \vskip\wd0 \vskip-\ht0
+\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}
 \caption/f Complete receiver block schematic of dual antenna interferometric station.
 \endinsert
 % doplnit schema skutecne pouziteho systemu
 An interfacing problem will by  probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to increased demand of embedded technologies, which requires high computation capacity, low power consumption and small size -- especially smart phones. Many of those ARM based systems has interesting parameters for signal processing. This facts makes Intel's ix86 architecture unattractive for future project.
 \sec Parralella board computer
-Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores,  Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM,  85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running.
+Parallella is new product from Adapteva, Inc. \cite[parallella-board], this small supercomputer have been in development almost two years and only testing series of boards have been produced until now (first single-board computers with 16-core Epiphany chip were shipped December 2013) \cite[parallella-board]. This board have near ideal parameters for signal processing (provides around 50 GFLOPS of computational power). The board is equipped by Epiphany coprocessor which has 16 High Performance RISC CPU Cores,  Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and 866 MHz operating frequency, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition of that this board consume only 3 Watts of power if both Zynq and Epiphany cores are running.
 Main disadvantage of Parralella board is is unknown lead time and absence of SATA interface or other interface for data storage connection. Fast data storage interface would be useful and allows bulk processing of captured data. Then a result from data processing will be sent over the Ethernet interface to data storage server.
 \midinsert
 \clabel[img-parallella-board]{Parallella board overview}
 \clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
 \picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
 \caption/f The NVIDIA Jetson TK1 Development Kit \url{https://developer.nvidia.com/jetson-tk1}.
 \endinsert
+NVIDIA board is discrict by presence of PCI Experess connector. This connector should be used for FPGA connection, if we decide to use this development board in our radio astronomy digitalisation system. A new FPGA board with PCI Express  direct PCB connector
+% doplnit popis pripojeni FPGA desky s HDMI Kabelem.
+\sec Other ARM based computation systems
+Other embeded ARM based computers for example ODROID-XU, lack of suitable high speed interface. Theirs highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing.
+From summary analysis mentioned above the Parrallella board should be the best candidate for computational board in radioastronomy data aquisition system. Parralella board is optimised for high data flow processing. Parallella has not much memory to cache processing data but instead of this it has wide bandwidth data channels. Other boards provides much more computational power -- 300 GFLOPS in case of NVIDIA K1, but these boards are optimised for computational heavy tasks on limited amount of data. This is typical problem in computer graphics. But in our application we do not need such extreme computation power at data aquisition system level.
+As result we should wait until Parallella becomes widely available. Then new ADCdual interfacing board should be designed ad prepared for use in new scalable radio astronomy data aquisition system. In meen time before suitable computing hardware become accessible. Required applications and algorithms should be optimised on proposed trial design with FPGA development board on standard PC host computer with PCI Express interface to development board.

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