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Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal.
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Interactive graber wiewer user interface shows live osciloscope-like time-value display for all data channels and live time-frequency scrolling display (waterfall wiev) for displaying frequency components of grabbed signal.
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\secc ADC module parameters
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\secc ADC module parameters
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Two pieces of ADC module design were realised and tested first piece denoted as ADC1 has LTC21190
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ADC chip populated with LT660015 front-end operational apmlifier. This ADC1 module has 1kOhm resistors populated on inputs which gives to module internal attenuation of input signal. Value of this attenuation is described by formula
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LTC21190
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
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\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.
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660015
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\endinsert
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1k
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T
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ADC1 CH1  maximal input 705.7 mV
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ADC1 CH1  maximal input 705.7 mV
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\midinsert
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\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png
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\caption/f Sine signal from ADC1 module with LTC21190 and LT6600-5 devices.
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\endinsert
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LTC2271
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LTC2271
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6600125
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6600125
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1k
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1k
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ADC2 CH1 maximal input 380 mV
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ADC2 CH1 maximal input 380 mV
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\sec Future improvements
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Several ADC module imperfections such as useless separation of FRAME and DCO signal to two connectors should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest.
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%\chap Example of usage
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%\chap Example of usage
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%\sec Simple polarimeter station
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%\sec Simple polarimeter station
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%\sec Basic interferometer station
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%\sec Basic interferometer station
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\chap Conclusion
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\chap Conclusion
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Special design of scalable data-aquisition system was proposed. This system has parameters
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Special design of scalable data-aquisition system was proposed. This system has parameters
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\sec Possible future improvements
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Several ADC module imperfections such as useless separation of FRAME and DCO signal to two connectors should be mitigated. And this two signals should be merged to one SATA connector. This modification removes one redundant SATA cable between analog to digital converter nest and between computational unit nest.