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Serial LVDS has been selected because uses lowest number of differencial pairs. This parameter is mandatory for construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}
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Serial LVDS has been selected because uses lowest number of differencial pairs. This parameter is mandatory for construction complexity and reliability. \url{http://www.ti.com/lit/pdf/snaa110}
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An ultrasound AFE chips should be ideal for this purpose -- this chips has front-end amplifiers and filters integrated. But theirs drawback is incapability of handling differential input signal and relatively low dynamic range (consists 12bit ADC). This IO has many ADC channels thus scalling are possible in factor of 4 receivers (8 analog channels).
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An ultrasound AFE chips should be ideal for this purpose -- this chips has front-end amplifiers and filters integrated. But theirs drawback is incapability of handling differential input signal and relatively low dynamic range (consists 12bit ADC). This IO has many ADC channels thus scalling are possible in factor of 4 receivers (8 analog channels).
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If we reduce range of usable chips by requirement of separate output for every analog channel and 16bit deph. Only several ADCs currently exists.
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If we require separate output for every analog channel and 16bit deph. Only several ADCs currently exists which meet these requirements.
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\begitems
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\begitems
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*[[http://www.linear.com/product/LTC2271|LTC2271]]
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*[[http://www.linear.com/product/LTC2271|LTC2271]]
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*[[http://www.linear.com/product/LTC2191|LTC2190-2195]].
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*[[http://www.linear.com/product/LTC2191|LTC2190-2195]].
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\enditems
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\enditems
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All parts in this category are compatible with one board layout.
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All parts in this category are compatible with one board layout. Main differences are in sampling frequency and signal to noise ratio. The slowest one has maximal sampling frequency 20 MHz. But all types have minimal sampling frequency 5 MSPS. All types were configurable over serial interface (SPI). SPI seems to be a standard for high-end ADC chips from main manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..).
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\secc ADC modules interface
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\secc ADC modules interface
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All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3.
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All two ADCdual01A modules was connected to FPGA ML605 board trough FMC2DIFF01A adapter board. Construction of this adapter module suppose FMC LPC connector. And this board is not MLAB compatible design. But this board is designed to meet VITA 57 standard specification for boards which uses zone 1 and zone 3.
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This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix.
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This specification guarantee compatibility with others FPGA board which has FMC LPC connector for mezzane cards. Schematic diagram of this adapter board is included in appendix.
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