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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalisation of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System. 
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The whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalisation of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays. This design will eventually become a part of MLAB Advanced Radio Astronomy System. 
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\sec Required parameters
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\sec Required parameters
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Wide dynamical range and high 3 intercept points are desired. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise.    
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Wide dynamical range and high IP3 are desired. The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise.    
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Summary of main required parameters follows 
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\begitems
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\begitems
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  * Dynamical range better than 80 dB
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  * Dynamical range better than 80 dB
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  * Phase stability between channels 
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  * Phase stability between channels 
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  * Noise (all types)
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  * Noise (all types)
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  * Sampling jitter better than 100 metres
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  * Sampling jitter better than 100 metres
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  * Support for any number of receivers in range 1 to 8
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\enditems
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\enditems
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\sec Sampling frequency
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\sec Sampling frequency
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Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1 MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.  
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Sampling frequency is limited by the technical constrains in the trial design. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1 MSPS leads to need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5 MSPS.
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We calculate minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5MSPS as $8 * 2 * 5e6 = 80$ MiB/s. Such data rate is at the limit of real writing speed o classical HDD and it is almost double of real bandwidth of USB 2.0 interface. 
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\sec System scalability
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\sec System scalability
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For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each I/Q channel in ADC module. ADC module must also have separate inputs for sampling and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. 
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For analogue channels scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. 
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.).
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Clock signal will be handled distinctively in our scalable design. Selected ADC chip are guaranteed to have defined clock skew between sampling and data output clock. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.).
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.     
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This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power.  There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.     
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We have used a centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used, while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used a centralised topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used, while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS disciplined control loop for frequency stabilisation.\fnote{\url{http://wiki.mlab.cz/doku.php?id=en:gpsdo} SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the diploma thesis.}
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging. 
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We have used methods of frequency monitoring compensation in order to meet modern requirements on radioastronomy equipment which needs precise frequency and phase stability over a wide scale for effective radioastronomy imaging. 
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. 
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Every ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from main local oscillator.  This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. 
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GPSDO design included in data acquisition system has special feature -- generates time marks for precise time-stamping of received signal. Timestamps are created by disabling of local oscillator for 100 us as result rectangle click in input signal is created which appears as horizontal line in spectrogram.   
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Timestamps should be seen in image \ref[meteor-reflection] (above and below meteor reflection).
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Time-marking should be improved in future by digitalisation GPS signal directly with dedicated ADC channel.  Datafile then consists samples from channels of radio-astronomy receivers along with GPS signal containing precise time information. 
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\secc Signal cable connectors 
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\secc Signal cable connectors 
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design. 
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Several widely used and commercially easily accessible differential connectors were considered to be use in our design. 
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\begitems
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\begitems
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6600125
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1k
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ADC2 CH1 maximal input 380 mV
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ADC2 CH1 maximal input 380 mV
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$$
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D.R. = N * b * 
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$$
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Where is 
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\begitems
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  * N - number of receivers
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  * Mi
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\enditems
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%\chap Example of usage
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\chap Example of usage
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%\sec Simple polarimeter station
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%\sec Simple polarimeter station
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%\sec Basic interferometer station
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\sec Basic interferometer station
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For system evaluation basic interferometry station was constructed.
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\midinsert
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\clabel[meteor-reflection]{Meteor reflection}
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\picw=10cm \cinspic ./img/screenshots/observed_meteor.png
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\caption/f Meteor reflection received by evaluation setup.
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\endinsert
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\midinsert
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\clabel[phase-phase-difference]{Phase difference}
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\picw=10cm \cinspic ./img/screenshots/phase_difference.png
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\caption/f Demonstration of phase difference between antennas.
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\endinsert
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\midinsert
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\clabel[block-schematic]{Receiver block schematic}
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\picw=10cm \cinspic ./img/Coherent_UHF_SDR_receiver.png
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\caption/f Complete receiver block schematic of dual antenna interferometric station.
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\endinsert
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%\sec Simple passive Doppler radar
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%\sec Simple passive Doppler radar
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\chap Proposed final system
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\chap Proposed final system
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