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\Xpage{-6}
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\Xpage{1}
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\Xpage{1}
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\Xchap{1}{Introduction }{1}
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\Xchap{1}{Introduction }{1}
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\Xsec{1.1}{Current radioastronomy problems }{1}
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\Xsec{1.2}{Typical Radio astronomy receiver }{1}
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\Xsec{1.1}{Typical Radio astronomy receiver }{1}
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\Xsec{1.3}{Requirements }{1}
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\Xsec{1.2}{Requirements }{1}
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\Xsecc{1.3.1}{Sensitivity }{1}
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\Xsecc{1.2.1}{Sensitivity }{1}
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\Xsecc{1.3.2}{Dynamic range }{1}
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\Xsecc{1.2.2}{Dynamic range }{1}
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\Xsecc{1.3.3}{Bandwidth }{1}
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\Xsecc{1.2.3}{Bandwidth }{1}
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\Xsec{1.4}{System requirements }{1}
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\Xsec{1.3}{Current radioastronomy problems }{1}
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\Xpage{2}
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\Xpage{2}
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\Xchap{2}{Testing construction }{2}
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\Xchap{2}{Testing construction }{2}
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\Xsec{2.1}{Required parameters }{2}
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\Xsec{2.1}{Required parameters }{2}
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\Xsec{2.2}{Sampling frequency }{2}
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\Xsec{2.2}{Sampling frequency }{2}
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\Xsec{2.3}{System scalability }{2}
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\Xsec{2.3}{System scalability }{2}
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\Xpage{4}
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\Xpage{4}
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\Xsec{2.4}{System description }{4}
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\Xsec{2.4}{System description }{4}
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\Xsecc{2.4.1}{Frequency synthesis }{4}
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\Xsecc{2.4.1}{Frequency synthesis }{4}
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\Xfnote
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\Xfnote
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\Xsecc{2.4.2}{Signal connectors }{4}
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\Xsecc{2.4.2}{Signal connectors }{4}
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\Xsecc{2.4.3}{Design of ADC modules }{4}
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\Xpage{5}
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\Xpage{5}
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\Xsecc{2.4.3}{Design of ADC modules }{5}
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\Xsecc{2.4.4}{ADC modules interface }{5}
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\Xsecc{2.4.4}{ADC selection }{5}
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\Xpage{6}
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\Xpage{6}
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\Xsecc{2.4.5}{Output data format }{6}
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\Xsecc{2.4.5}{ADC modules interface }{6}
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\Xsec{2.5}{Achieved parameters }{6}
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\Xsecc{2.5.1}{Data reading and recording }{6}
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\Xpage{7}
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\Xsecc{2.4.6}{Output data format }{7}
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\Xsec{2.6}{Future improvements }{7}
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\Xsec{2.5}{Achieved parameters }{7}
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\Xpage{8}
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\Xpage{8}
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\Xchap{3}{Proposed final system }{8}
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\Xsec{3.1}{Custom design of FPGA board }{8}
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\Xsecc{2.5.1}{Data reading and recording }{8}
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\Xsec{3.2}{Parralella board computer }{8}
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\Xsecc{2.5.2}{ADC module parameters }{8}
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\Xsec{3.3}{GPU based computational system }{8}
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\Xchap{4}{Conclusion }{9}
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\Xchap{A}{Circuit diagram of ADCdual01A module }{11}
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\Xchap{3}{Proposed final system }{11}
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\Xsec{3.1}{Custom design of FPGA board }{11}
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\Xsec{3.2}{Parralella board computer }{11}
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\Xsec{3.3}{GPU based computational system }{11}
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\Xchap{4}{Conclusion }{12}
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\Xsec{4.1}{Possible future improvements }{12}
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\Xpage{13}
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\Xchap{A}{Circuit diagram of ADCdual01A module }{13}
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\Xpage{14}
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\Xchap{B}{Circuit diagram of FMC2DIFF module }{12}
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\Xchap{B}{Circuit diagram of FMC2DIFF module }{14}