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\Xpage{7}
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\Xpage{7}
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\Xsecc{2.4.6}{Output data format }{7}
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\Xsecc{2.4.6}{Output data format }{7}
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\Xsec{2.5}{Achieved parameters }{7}
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\Xsec{2.5}{Achieved parameters }{7}
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\Xpage{8}
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\Xpage{8}
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\Xsecc{2.5.1}{Data reading and recording }{8}
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\Xsecc{2.5.1}{Data reading and recording }{8}
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\Xsecc{2.5.2}{ADC module parameters }{8}
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\Xpage{9}
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\Xpage{9}
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\Xsecc{2.5.2}{ADC module parameters }{9}
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\Xpage{10}
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\Xpage{10}
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\Xpage{11}
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\Xpage{11}
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\Xchap{3}{Proposed final system }{11}
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\Xchap{3}{Proposed final system }{11}
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\Xsec{3.1}{Custom design of FPGA board }{11}
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\Xsec{3.1}{Custom design of FPGA board }{11}
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\Xsec{3.2}{Parralella board computer }{11}
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\Xsec{3.2}{Parralella board computer }{11}