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\Xpage{-6}
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\Xpage{-6}
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\Xpage{1}
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\Xpage{1}
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\Xchap{1}{Introduction }{1}
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\Xchap{1}{Introduction }{1}
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\Xsec{1.1}{Modern Radio astronomy receiver }{1}
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\Xsec{1.1}{Current radioastronomy problems }{1}
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\Xsecc{1.1.1}{Observation types }{1}
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\Xpage{2}
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\Xpage{2}
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\Xsec{1.2}{Requirements }{2}
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\Xsecc{1.2.1}{Sensitivity and noise number }{2}
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\Xsecc{1.2.2}{Dynamic range }{2}
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\Xsecc{1.2.3}{Bandwidth }{2}
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\Xsec{1.3}{Current radioastronomy problems }{2}
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\Xsec{1.2}{Modern Radio astronomy receiver }{2}
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\Xpage{3}
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\Xpage{3}
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\Xchap{2}{Testing construction }{3}
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\Xsecc{1.2.1}{Observation types }{3}
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\Xsec{2.1}{Required parameters }{3}
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\Xsec{1.3}{Required receiver parameters }{3}
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\Xsecc{1.3.1}{Sensitivity and noise number }{3}
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\Xsec{2.2}{Sampling frequency }{3}
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\Xsecc{1.3.2}{Dynamic range }{3}
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\Xsecc{1.3.3}{Bandwidth }{3}
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\Xpage{4}
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\Xpage{4}
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\Xchap{2}{Testing construction }{4}
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\Xsec{2.1}{Required parameters }{4}
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\Xsec{2.2}{Sampling frequency }{4}
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\Xsec{2.3}{System scalability }{4}
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\Xsec{2.3}{System scalability }{4}
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\Xsecc{2.3.1}{Differential signalling }{4}
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\Xpage{5}
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\Xsecc{2.3.1}{Differential signalling }{5}
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\Xsecc{2.3.2}{Phase matching }{5}
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\Xsecc{2.3.2}{Phase matching }{5}
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\Xsec{2.4}{System description }{5}
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\Xsec{2.4}{System description }{5}
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\Xsecc{2.4.1}{Frequency synthesis }{5}
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\Xsecc{2.4.1}{Frequency synthesis }{5}
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\Xfnote
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\Xfnote
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\Xsecc{2.4.2}{Signal cable connectors }{5}
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\Xsecc{2.4.2}{Signal cable connectors }{5}
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\Xpage{6}
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\Xpage{6}
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\Xfig{img-miniSAS-cable}{2.1}{Used miniSAS cable}
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\Xfig{img-miniSAS-cable}{2.1}{Used miniSAS cable}
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\Xlabel{img-miniSAS-cable}{2.1}
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\Xlabel{img-miniSAS-cable}{2.1}
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\Xsecc{2.4.3}{Signal integrity requirements }{6}
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\Xsecc{2.4.3}{Signal integrity requirements }{6}
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\Xsecc{2.4.4}{Design of ADC modules }{6}
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\Xpage{7}
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\Xpage{7}
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\Xsecc{2.4.4}{Design of ADC modules }{7}
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\Xsecc{2.4.5}{ADC selection }{7}
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\Xsecc{2.4.5}{ADC selection }{7}
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\Xpage{8}
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\Xtab{ADC-types}{2.1}{Available ADC types}
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\Xtab{ADC-types}{2.1}{Available ADC types}
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\Xlabel{ADC-types}{2.1}
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\Xlabel{ADC-types}{2.1}
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\Xpage{8}
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\Xsecc{2.4.6}{ADC modules interface }{8}
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\Xsecc{2.4.6}{ADC modules interface }{8}
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\Xsecc{2.4.7}{Output data format }{8}
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\Xsec{2.5}{Achieved parameters }{8}
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\Xpage{9}
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\Xpage{9}
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\Xsecc{2.4.7}{Output data format }{9}
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\Xsecc{2.5.1}{Data reading and recording }{9}
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\Xsec{2.5}{Achieved parameters }{9}
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\Xsecc{2.5.2}{ADC module parameters }{9}
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\Xpage{10}
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\Xpage{10}
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\Xsecc{2.5.1}{Data reading and recording }{10}
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\Xsecc{2.5.2}{ADC module parameters }{10}
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\Xpage{11}
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\Xpage{11}
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\Xpage{12}
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\Xpage{12}
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\Xchap{3}{Proposed final system }{12}
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\Xsec{3.1}{Custom design of FPGA board }{12}
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\Xsec{3.2}{Parralella board computer }{12}
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\Xsec{3.3}{GPU based computational system }{12}
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\Xpage{13}
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\Xchap{3}{Proposed final system }{13}
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\Xsec{3.1}{Custom design of FPGA board }{13}
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\Xsec{3.2}{Parralella board computer }{13}
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\Xpage{14}
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\Xsec{3.3}{GPU based computational system }{14}
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\Xfig{img-NVIDIA-K1}{3.1}{NVIDIA Jetson TK1 Development Kit}
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\Xfig{img-NVIDIA-K1}{3.1}{NVIDIA Jetson TK1 Development Kit}
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\Xlabel{img-NVIDIA-K1}{3.1}
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\Xlabel{img-NVIDIA-K1}{3.1}
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\Xpage{14}
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\Xchap{4}{Conclusion }{14}
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\Xsec{4.1}{Possible future improvements }{14}
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\Xpage{15}
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\Xpage{15}
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\Xchap{4}{Conclusion }{15}
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\Xchap{A}{Circuit diagram of ADCdual01A module }{15}
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\Xpage{16}
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\Xsec{4.1}{Possible future improvements }{15}
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\Xchap{B}{Circuit diagram of FMC2DIFF module }{16}
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\Xpage{17}
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\Xchap{A}{Circuit diagram of ADCdual01A module }{17}
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\Xpage{18}
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\Xchap{B}{Circuit diagram of FMC2DIFF module }{18}
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