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\Xsecc{1.3.2}{Dynamic range }{3}
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\Xsecc{1.3.2}{Dynamic range }{3}
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\Xtab{ADC-dynamic-range}{1.1}{Dynamic range versus bit depth}
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\Xtab{ADC-dynamic-range}{1.1}{Dynamic range versus bit depth}
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\Xlabel{ADC-dynamic-range}{1.1}
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\Xlabel{ADC-dynamic-range}{1.1}
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\Xsecc{1.3.3}{Bandwidth }{3}
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\Xsecc{1.3.3}{Bandwidth }{3}
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\Xpage{4}
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\Xpage{4}
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\Xchap{2}{Trial design }{4}
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\Xsec{2.1}{Required parameters }{4}
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\Xsec{1.4}{Current status of receivers digitalization units }{4}
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\Xsec{2.2}{Sampling frequency }{4}
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\Xsecc{1.4.1}{Custom digitalization system }{4}
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\Xsec{2.3}{System scalability }{4}
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\Xsecc{1.4.2}{Modular digitalization systems }{4}
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\Xpage{5}
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\Xpage{5}
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\Xsecc{2.3.1}{Differential signalling }{5}
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\Xsecc{2.3.2}{Phase matching }{5}
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\Xsec{2.4}{System description }{5}
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\Xsecc{2.4.1}{Frequency synthesis }{5}
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\Xfnote
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\Xpage{6}
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\Xpage{6}
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\Xchap{2}{Trial design }{6}
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\Xsecc{2.4.2}{Signal cable connectors }{6}
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\Xsec{2.1}{Required parameters }{6}
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\Xsecc{2.4.3}{Signal integrity requirements }{6}
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\Xsec{2.2}{Sampling frequency }{6}
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\Xsecc{2.4.4}{ADC modules design }{6}
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\Xsec{2.3}{System scalability }{6}
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\Xpage{7}
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\Xpage{7}
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\Xsecc{2.3.1}{Differential signaling }{7}
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\Xsecc{2.3.2}{Phase matching }{7}
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\Xsec{2.4}{System description }{7}
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\Xsecc{2.4.1}{Frequency synthesis }{7}
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\Xfnote
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\Xpage{8}
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\Xsecc{2.4.2}{Signal cable connectors }{8}
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\Xsecc{2.4.3}{Signal integrity requirements \immediate \write 16{l.99 OPmac WARNING: duplicated label [diff-signaling], ignored.}\ignorespaces  }{8}
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\Xlabel{diff-signaling}{2.4.4}
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\Xsecc{2.4.4}{ADC modules design }{8}
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\Xsecc{2.4.5}{ADC selection }{8}
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\Xpage{9}
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\Xfig{img-miniSAS-cable}{2.1}{Used miniSAS cable}
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\Xfig{img-miniSAS-cable}{2.1}{Used miniSAS cable}
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\Xlabel{img-miniSAS-cable}{2.1}
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\Xlabel{img-miniSAS-cable}{2.1}
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\Xsecc{2.4.5}{ADC selection }{7}
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\Xpage{8}
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\Xpage{10}
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\Xtab{ADC-types}{2.1}{Available ADC types}
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\Xtab{ADC-types}{2.1}{Available ADC types}
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\Xlabel{ADC-types}{2.1}
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\Xlabel{ADC-types}{2.1}
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\Xsecc{2.4.6}{ADC modules interface }{8}
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\Xsecc{2.4.7}{Output data format }{8}
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\Xsec{2.5}{Achieved parameters }{8}
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\Xpage{9}
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\Xfig{VITA57-regions}{2.3}{VITA57 board geometry}
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\Xfig{1-line-out}{2.2}{Single line ADC output signals}
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\Xlabel{VITA57-regions}{2.3}
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\Xlabel{1-line-out}{2.2}
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\Xsecc{2.5.1}{Data reading and recording }{9}
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\Xpage{10}
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\Xpage{11}
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\Xpage{11}
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\Xsecc{2.5.2}{ADC module parameters }{11}
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\Xsecc{2.4.6}{ADC modules interface }{11}
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\Xpage{12}
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\Xpage{12}
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\Xfig{VITA57-regions}{2.4}{VITA57 board geometry}
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\Xlabel{VITA57-regions}{2.4}
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\Xsecc{2.4.7}{Output data format }{12}
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\Xsec{2.5}{Achieved parameters }{12}
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\Xsecc{2.5.1}{Data reading and recording }{12}
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\Xsecc{2.5.2}{ADC module parameters }{12}
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\Xpage{13}
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\Xpage{13}
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\Xchap{3}{Example of usage }{13}
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\Xsec{3.1}{Basic interferometer station }{13}
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\Xfig{meteor-reflection}{3.1}{Meteor reflection}
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\Xlabel{meteor-reflection}{3.1}
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\Xfig{phase-phase-difference}{3.2}{Phase difference}
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\Xlabel{phase-phase-difference}{3.2}
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\Xpage{14}
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\Xpage{14}
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\Xfig{block-schematic}{3.3}{Receiver block schematic}
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\Xfig{ADC1-FFT}{2.7}{ADC1 sine test FFT}
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\Xlabel{block-schematic}{3.3}
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\Xlabel{ADC1-FFT}{2.7}
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\Xpage{15}
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\Xpage{15}
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\Xchap{4}{Proposed final system }{15}
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\Xfig{ADC2-FFT}{2.8}{ADC2 sine test FFT}
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\Xsec{4.1}{Custom design of FPGA board }{15}
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\Xsec{4.2}{Parralella board computer }{15}
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\Xlabel{ADC2-FFT}{2.8}
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\Xsec{4.3}{GPU based computational system }{15}
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\Xpage{16}
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\Xpage{16}
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\Xchap{3}{Example of usage }{16}
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\Xsec{3.1}{Basic interferometer station }{16}
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\Xfig{img-NVIDIA-K1}{4.1}{NVIDIA Jetson TK1 Development Kit}
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\Xfig{block-schematic}{3.1}{Receiver block schematic}
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\Xlabel{img-NVIDIA-K1}{4.1}
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\Xlabel{block-schematic}{3.1}
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\Xpage{17}
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\Xpage{17}
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\Xfig{meteor-reflection}{3.2}{Meteor reflection}
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\Xlabel{meteor-reflection}{3.2}
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\Xfig{phase-phase-difference}{3.3}{Phase difference}
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\Xlabel{phase-phase-difference}{3.3}
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\Xpage{18}
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\Xchap{5}{Conclusion }{17}
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\Xchap{4}{Proposed final system }{18}
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\Xsec{4.1}{Custom design of FPGA board }{18}
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\Xsec{5.1}{Possible future improvements }{17}
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\Xsec{4.2}{Parralella board computer }{18}
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\Xsec{4.3}{GPU based computational system }{18}
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\Xpage{19}
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\Xpage{19}
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\Xchap{A}{Circuit diagram of ADCdual01A module }{19}
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\Xfig{img-NVIDIA-K1}{4.1}{NVIDIA Jetson TK1 Development Kit}
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\Xlabel{img-NVIDIA-K1}{4.1}
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\Xpage{20}
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\Xpage{20}
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\Xchap{5}{Conclusion }{20}
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\Xchap{B}{Circuit diagram of FMC2DIFF module }{20}
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\Xsec{5.1}{Possible future improvements }{20}
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\Xpage{21}
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\Xpage{21}
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\Xchap{A}{Circuit diagram of ADCdual01A module }{21}
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\Xpage{22}
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\Xpage{22}
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\Xchap{B}{Circuit diagram of FMC2DIFF module }{22}
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\Xpage{23}
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\Xpage{23}
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\Xpage{24}
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\Xpage{24}
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\Xpage{25}
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\Xpage{26}
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\Xpage{27}
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\Xchap{C}{Content of enclosed CD }{27}