| 3 |
The trial version construction was tested for proper handling of sampling rates in the range of 5 MSPS to 15 MSPS, but it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system. Data recording of input signal is impossible above the sampling rates around 7 MSPS due to bottleneck at HDD speed limits, but it should be resolved by the use of SSD disk drive. However, such design has not been tested in our setup.
|
3 |
The trial version construction was tested for proper handling of sampling rates in the range of 5 MSPS to 15 MSPS, but it should work even above this limit. The system works on i7 8 cores computer with Ubuntu 12.04 LTS operating system. Data recording of input signal is impossible above the sampling rates of around 7 MSPS due to bottleneck at HDD speed limits, but it should be resolved by the use of SSD disk drive. However, such design has not been tested in our setup.
|
| 7 |
Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is calculated by the following formula \ref[ADC1-gain]
|
7 |
Two prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is calculated by the following formula \ref[ADC1-gain]
|