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\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
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\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}
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\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
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\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg
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\caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1].
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\caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1].
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\endinsert
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\endinsert
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NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express should be used for FPGA connection. A new FPGA board with PCI Express direct PCB connector
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NVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express should be used for FPGA connection. A new custom design of FPGA board with Half mini-PCIE direct connector on PCB edge is impractical interface solution due to geometric constrains. Instead of this, the new FPGA module should be designed in standard MLAB fashion and connected to NVIDIA Jetson TK1 via miniHDMI cable. Similar connection solution can be found in source \cite[fmc-sata].
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% doplnit popis pripojeni FPGA desky s HDMI Kabelem.
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% doplnit popis pripojeni FPGA desky s HDMI Kabelem.
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\sec Other ARM based computation systems
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\sec Other ARM based computation systems
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Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing.
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Other embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface \cite[mlab-arm]. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing.
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From the summary analysis mentioned above, the Parrallella board seems to be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level.
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From the summary analysis mentioned above, the Parrallella board seems to be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level.
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As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial version with FPGA development board on standard PC host computer (having a PCI Express interface to development board).
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As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial version with FPGA development board on standard PC host computer (having a PCI Express interface to development board).
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