Subversion Repositories svnkaklik

Rev

Rev 1142 | Rev 1147 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log

Rev 1142 Rev 1145
Line 83... Line 83...
83
\caption/f Complete receiver block schematic of dual antenna interferometric station.
83
\caption/f Complete receiver block schematic of dual antenna interferometric station.
84
\endinsert
84
\endinsert
85
 
85
 
86
% doplnit schema skutecne pouziteho systemu
86
% doplnit schema skutecne pouziteho systemu
87
 
87
 
88
Despite of the schematic diagram proposed at beginning of system description....
88
Despite of the schematic diagram proposed at beginning of system description \ref[expected-block-schematic].
89
We have used two separate oscillators -- one oscillator drives encoded signal to ADCs still through FPGA based divider and the other one drives it to SDRX01B mixer.
89
We have used two separate oscillators -- one oscillator drives encoded signal to ADCs still through FPGA based divider and the other one drives it to SDRX01B mixer.
90
The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
90
The reason for this modification was an attempt to simplify the frequency tuning during the experiment. A single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.
91
We have used ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.
91
We have used ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.
92
 
92
 
93
\midinsert
93
\midinsert