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(root)//Designs/HAM_Constructions/SDRX02A/HDL/modules/sychro1/up_counter.vhd @ 4978

Rev 4962

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity up_counter is
generic (
        
        G_MIN_NUMBER : natural := 0;
        G_MAX_NUMBER : natural := 10
        
        );
port (

        i_clk   : in std_logic;
        i_rst : in std_logic;
        
  -- Count when this input is '1'
  i_valid : in std_logic;
   
   -- Output the actual number
        o_data : out natural := G_MIN_NUMBER;
        o_carry : out std_logic := '0'
        
   );
end up_counter;

architecture rtl of up_counter is

signal number : natural range G_MIN_NUMBER to G_MAX_NUMBER := G_MIN_NUMBER;

begin

        o_data <= number;
        
        counter : process( i_clk )
        begin
        
                if( rising_edge( i_clk ) ) then
                
                        o_carry <= '0';
                
                        if( i_rst = '1' ) then
                                number <= G_MIN_NUMBER;
                        elsif( i_valid = '1' ) then
                                -- count up:
                                if( number = G_MAX_NUMBER ) then
                                        number <= G_MIN_NUMBER;
                                        o_carry <= '1';
                                else
                                        number <= number + 1;
                                end if;
                                
                        end if;
                end if;
        end process;
                                        
end architecture;