-- Dummy user_logic_cmp_winfo
--
--
-- Uses only data1 stream and simply adds to each byte a given number
--
-- uses the information_block entity for version/type control

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity user_logic_cmp is
port (
        i_clk : in std_logic;
        i_rst : in std_logic;
        
        -- data1 interface:
        i_data1in_data          : in std_logic_vector( 31 downto 0 );
        i_data1in_valid   : in std_logic;
        o_data1in_enable        : out std_logic;
        o_data1out_data         : out std_logic_vector( 31 downto 0 );
        o_data1out_valid        : out std_logic;
        i_data1out_enable       : in std_logic;
        
        -- data2 interface:
        i_data2in_data          : in std_logic_vector( 31 downto 0 );
        i_data2in_valid   : in std_logic;
        o_data2in_enable        : out std_logic;
        o_data2out_data         : out std_logic_vector( 31 downto 0 );
        o_data2out_valid        : out std_logic;
        i_data2out_enable       : in std_logic;
        
        -- control interface:
        i_controlin_data                : in std_logic_vector( 31 downto 0 );
        i_controlin_valid   : in std_logic;
        o_controlin_enable      : out std_logic;
        o_controlout_data       : out std_logic_vector( 31 downto 0 );
        o_controlout_valid      : out std_logic;
        i_controlout_enable     : in std_logic
        
);
end entity;

architecture behavioral of user_logic_cmp is

        component information_block is
        port (
                clk : in std_logic; rst : in std_logic;
                -- Input side:
                i_data   : in  std_logic_vector( 31 downto 0 ); i_valid  : in  std_logic; o_enable : out std_logic;
                -- Output side:
                o_data   : out std_logic_vector( 31 downto 0 ); o_valid  : out std_logic; i_enable : in  std_logic );
        end component;

begin

        -- Example how to read and transmit data:
        sum_process : process( i_clk )
        begin
                if( rising_edge( i_clk ) ) then
                        if( i_rst = '1' ) then
                                o_data1out_data <= ( others => '0' );
                                o_data1out_valid <= '0';
                        else
                                o_data1out_data( 31 downto 24 ) <= std_logic_vector( unsigned(i_data1in_data( 31 downto 24 )) + to_unsigned(1,8) );
                                o_data1out_data( 23 downto 16 ) <= std_logic_vector( unsigned(i_data1in_data( 23 downto 16 )) + to_unsigned(2,8) );
                                o_data1out_data( 15 downto  8 ) <= std_logic_vector( unsigned(i_data1in_data( 15 downto  8 )) + to_unsigned(3,8) );
                                o_data1out_data(  7 downto  0 ) <= std_logic_vector( unsigned(i_data1in_data(  7 downto  0 )) + to_unsigned(4,8) );
                                o_data1out_valid <= i_data1in_valid;
                        end if;
                end if;
        end process;
        o_data1in_enable <= i_data1out_enable;
        
        -- information_block:
        info_block_inst : information_block
        port map (
                clk => i_clk, rst => i_rst,
                i_data => i_controlin_data, i_valid => i_controlin_valid, o_enable => o_controlin_enable,
                o_data => o_controlout_data, o_valid => o_controlout_valid, i_enable => i_controlout_enable );
                
end architecture;