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\chap Trial version of the receiver, design and implementationThe whole design of radioastronomy receiver digitalization unit is constructed to be used in a wide range of applications and tasks related to digitalization of signal from radioastronomy receivers. A good illustrating problem for its use is a signal digitalisation from multiple antenna arrays.\midinsert\clabel[expected-block-schematic]{Expected system block schematic}\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Coherent_UHF_SDR_receiver.png }\par\nobreak \vskip\wd0 \vskip-\ht0\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}\caption/f Expected realisation of signal digitalisation unit.\endinsert\sec Required parametersWe require the following technical parameters, to supersede existing digitalization units solutions.Primarily, we need wide a dynamical range and high IP3. \glos{IP3}{Third-order intercept point} The receiver must accept wide dynamic signals because a typical radioastronomical signal has a form of a weak signal covered by a strong man-made noise or other undesired noises as lighting, Sun emissions etc.Summary of other additional required parameters follows\begitems* Dynamical range better than 80 dB, see section \ref[dynamic-range-theory] for explanation* Phase stability between channels* Low noise (all types)* Sampling jitter better than 100 metres* Support for any number of receivers in the range of 1 to 8\enditemsNow we analyze several of the parameters in detail.\sec Sampling frequencySampling frequency is not limited by the technical constrains in the trial version. This parameter is especially limited by the sampling frequencies of analog-to-digital conversion chips available on the market and interface bandwidth. Combination of the required parameters -- dynamic range requiring at least 16bit and a minimum sampling frequency of 1$\ $MSPS \glos{MSPS}{Mega-Samples Per Second} leads to the need of high end ADC chips which does not support such low sampling frequencies at all. Their minimum sampling frequency is 5$\ $MSPS.We calculated a minimum data bandwidth data rate for eight receivers, 2 bytes per sample and 5$\ $MSPS as $8 \cdot 2 \cdot 5\cdot 10^6 = 80\ $MB/s. Such data rate is at the limit of the actual writing speed of classical HDD \glos{HDD}{Hard disk drive} and it is almost double the real bandwidth of USB 2.0 \glos{USB 2.0}{Universal Serial Bus version 2.0} interface. As a result of these facts we must use faster interface. Faster interface is especially needed in cases where we require faster sampling rates than ADC's minimal 5$\ $MSPS sample rate.The most perspective interface for use in our type of application is USB 3.0 or PCI Express interface. However, USB 3.0 is a relatively new technology without good development tools currently available. We have used PCI Express \glos{PCI Express}{Peripheral Component Interconnect Express} interface as the simplest and the most reliable solution.\sec System scalabilityFor analogue channels' scalability, special parameters of ADC modules are required. Ideally, there should be a separate output for each analogue channel in ADC module. ADC module must also have separate outputs for frames and data output clocks. These parameters allow for conduction at relatively low digital data rates. As a result, the digital signal can be conducted even through long wires. Modular concept allows a separation from central logical unit which supports optimization of number analogue channels.Clock and data signals will be then handled distinctively in our modular scalable design. Selected ADC chips are guaranteed to have defined clock skew between the sampling and data output clocks. This allows taking data and frame clocks from the first ADC module only. The rest of the data and frame clocks from other ADC modules can be measured for diagnostic purposes (failure detection, jitter measurement etc.), but these redundant signals are not used for data sampling. If more robustness is required in the final application, DCO \glos{DCO}{Data Clock Output} and FR signals may be collected from other modules and routed through an voting logic which will correct possible signal defects.This system concept allows for scalability, that is technically limited by a number of differential signals on host side and its computational power. There is another advantage of scalable data acquisition system -- an economic one. Observatories or end users can make a choice of how much money are they willing to spent on radioastronomy receiver system. This freedom of choice is especially useful for science sites without previous experience in radioastronomy observations.\secc Differential signallingThe above mentioned concept of scalable design requires relatively long circuit traces between ADC and digital unit which captures the data and performs the computations. The long distance between the digital processing unit and the analog-to-digital conversion unit has an advantage in noise retention typically produced by digital circuits. Those digital circuits, such as FPGA \glos{FPGA}{Field-programmable gate array}, Ethernet or other flip-flops blocks and circuit traces, usually work at high frequencies and emit wide-band noise with relatively low power. In such cases any increase in a distance between the noise source and analog signal source increase S/N significantly. However, at the same time, a long distance brings problems with the digital signal transmission between ADC and computational unit. But this obstacle should be resolved more easily in free-space than on board routing. The high-quality differential signalling shielded cables should be used, such as massively produced and cheap SATA \glos{SATA}{Serial ATA} \glos{ATA}{AT Attachment} cables. This technology has two advantages over PCB \glos{PCB}{printed circuit board} signal routing. First, it can use twisted pair of wires for leak inductance suppression in signal path and second, the twisted pair may additionally be shielded by uninterrupted metal foil.\secc Phase matchingFor multiple antenna radioastronomy projects, system phase stability is a mandatory condition. It allows a precise, high resolution imaging of objects, increases signal to noise ratios in several observation methods and allows the use of advanced algorithms for signal processing.High phase stability in our scalable design is achieved through centralized frequency generation and distribution with multi-output LVPECL \glos{LVPECL}{Low Voltage Emitter-coupled logic} hubs (CLKHUB02A), that have equiphased outputs for multiple devices. LVPECL logic is used on every system critical clock signal distribution hub. LVPECL logic has an advantage over LVDS \glos{LVDS}{Low-voltage differential signaling} in signal integrity robustness. LVPECL uses higher logical levels and higher signalling currents. Power consumption of LVPECL logic is nearly constant over the operating frequency range due to the use of bipolar transistors. This minimizes voltage glitches which are typical for CMOS \glos{CMOS}{Complementary metal–oxide–semiconductor } logic. One drawback of its parameters is a high power consumption of LVPECL logic which easily reaches tens of milliamperes per device.This design ensures that all system devices have access to the defined phase and known frequency.\sec System descriptionThis section deals with the description of the trial version based on Xilinx ML605 development board \ref[ML605-development-board]. The board had been used in a previous project and has not been used since then, but the FPGA parameters are more than sufficient of what we need for fast data acquisition system.\secc Frequency synthesisWe have used a centralized topology as a basis for frequency synthesis. One precise high-frequency and low-jitter digital oscillator has been used \cite[MLAB-GPSDO], while other working frequencies have been derived from it by the division of its signal. This central oscillator has a software defined GPS \glos{GPS}{Global Positioning System} disciplined control loop for frequency stabilization.\fnote{SDGPSDO design has been developed in parallel to this diploma thesis as a related project, but it is not explicitly required by the thesis itself and thus it is described in a separate document}We have used new methods of software frequency monitoring and compensation in order to meet modern requirements on radioastronomy equipment which need precise frequency and phase stability over a wide baseline scales for effective radioastronomy imaging.The GPSDO device consists of Si570 chip with LVPECL output. Phase jitter of GPSDO \glos{GPSDO}{GPS disciplined oscillator} is determined mainly by Si570 phase noise. Parameters of the Si570 are summarized in the following table \ref[LO-noise] (source \cite[si570-chip] ).The GPSDO design, that is included in data acquisition system, has special feature -- it generates time marks for a precise time-stamping of the received signal. Timestamps are created by disabling the local oscillator's outputs, connected to SDRX01B receivers, for 100 us. As result, a rectangular click in the ADC input signal is created which appears as a horizontal line in spectrogram.Timestamps should be seen in image \ref[meteor-reflection] (above and below the meteor reflection).Time-marking should be improved in future by digitalization of GPS signal received by antenna on observational station. Following that, the GPS signal can be directly sampled by a dedicated receiver and one separate ADC module. Datafile then consists of samples from channels of radio-astronomy receivers along with the GPS signal containing precise time information.\midinsert \clabel[LO-noise]{Phase noise of the local oscillator}\ctable{lcc}{& \multispan2 \hfil Phase Noise [dBc/Hz] \hfil \crOffset Frequency & $F_{out}$ 156.25 MHz & $F_{out}$ 622.08 MHz \cr100 [Hz] & –105 & –97 \cr1 [kHz] & –122 & –107 \cr10 [kHz] & –128 & –116 \cr100 [kHz] & –135 & –121 \cr1 [MHz] & –144 & –134 \cr10 [MHz] & –147 & –146 \cr100 [MHz] & n/a & –148 \cr}\caption/t Phase noise of the used Silicon Laboratories Si570 chip. Offset frequency is measured from carrier frequency. Values shown in the table are given for two different carrier frequencies.\endinsertEvery ADC module will be directly connected to CLKHUB02A module which takes sampling clock signal delivered by FPGA from the main local oscillator. This signal should use high quality differential signalling cable -- we should use SATA cable for this purpose. FPGA may slightly affect the clock signal quality by adding a noise, but it has a negligible effect on the application where developed system will be used.\secc Signal cable connectors\label[signal-cables]Several widely used and commercially easily accessible differential connectors were considered to be use in our design.\begitems* HDMI % [[http://en.wikipedia.org/wiki/Hdmi|HDMI]]</del>* SATA %{http://en.wikipedia.org/wiki/Serial_attached_SCSI#Connectors|SAS]]/[[http://en.wikipedia.org/wiki/Serial_ATA|SATA]]* DisplayPort %[[http://en.wikipedia.org/wiki/Display_port|DisplayPort]]</del>* SAS/miniSAS\enditemsAt the end, MiniSAS connector was chosen as the best option to be used in connecting together multiple ADC modules. A transition between SATA and miniSAS is achieved by SAS to SATA adapter cable which is commonly used in servers to connect SAS controller to multiple SATA hard disc in RAID systems and thus is commercially easily available. It is compatible with existing SATA cabling systems and aggregates multiple SATA cables to a single connector. It also has SPI configuration lines which can be seen in the following picture \ref[img-miniSAS-cable] as standard pinheader connector.The main drawback of miniSAS PCB connectors lies in the fact, that they are manufactured in SMT versions only. SMT design may eventually decrease the durability of the connector even if outer metal housing of connector is designed to be mounted using a standard through-hole mounting method.\midinsert\clabel[img-miniSAS-cable]{Used miniSAS cable}\picw=5cm \cinspic ./img/miniSAS_SATA_cable.jpg\caption/f An example of miniSAS cable similar to used.\endinsert\secc Signal integrity requirements\label[diff-signaling]We use ADC devices that have DATA clock frequency eight times higher than sampling frequency in a single line output mode, implying a 40 MHz output bit rate. This implies a $ 1/4 \cdot 10^7 = 25\ $ns time length of data bit, which is equivalent to 7.5m light path in free space. If we use copper PCB with FR4 substrate layer or coaxial/twinax cable, we could obtain velocity factor of 0.66 at worst condition. Then the light path for the same bit rate $t_s$ will be 4.95 m. Although we do not have any cables in the system with comparable lengths, the worst data bit skew described by data sheets of the used components is $0.3 \cdot t_s$, which is 1.485 m. Therefore the length matching is not critical in our current design operating on lowest sampling speed. Length matching may become critical in future versions with higher sampling rates, where the cable length must be matched. However SATA cabling technology is already prepared for that case and matched SATA cables are a standard merchandise.\secc ADC modules design\midinsert\clabel[adcdual-preview]{Preview of designed ADCdual PCB}\picw=10cm \cinspic ./img/ADCdual01A_Top_Big.JPG\picw=10cm \cinspic ./img/ADCdual01A_Bottom_Big.JPG\caption/f Realised PCB of ADCdual01A modules. Differential pairs routings are clearly visible.\endinsert\secc ADC selectionThere exist several standard ADC signalling formats currently used in communication with FPGA.\begitems* DDR LVDS* JEDEC 204B* JESD204A* Paralel LVDS* Serdes* serial LVDS\enditemsAs a result of our need to use the smallest number of cables possible, the choice fell on the serial LVDS format. Small number of differential pairs is an important parameter determining the construction complexity and reliability\cite[serial-lvds]. No many currently existing ADC devices have this kind of digital interface. An ultrasound AFE device chips seem to be ideal for this purpose -- the chip has integrated both front-end amplifiers and filters. It has a drawback though - it is incapable of handling differential input signal and has a relatively low dynamic range (as it consists only of 12bit ADC) and has many single ended ADC channels. Consequently, the scaling is possible only by a factor of 4 receivers (making 8 analogue single ended channels).If we add a requirement of separate output for every analogue channel and a 16bit depth we find that there are only a few 2-Channel simultaneous sampling ADCs currently existing which meet these criteria. We have summarized those ADCs in the following table \ref[ADC-types]\midinsert\typosize[9/11] \def\tabiteml{ }\let\tabitemr=\tabiteml\clabel[ADC-types]{Available ADC types}\ctable{lccccccc}{\hfil ADC Type & LTC2271 & LTC2190 & LTC2191 & LTC2192 & LTC2193 & LTC2194 & LTC2195 \crSNR [dB] & 84.1 & 77 & 77 & 77 & 76.8 & 76.8 & 76.8 \crSFDR [dB] & 99 & 90 & 90 & 90 & 90 & 90 & 90 \crS/H Bandwidth [MHz] & 200 & \multispan6 550 \strut \crSampling rate [MSPS] & 20 & 25 & 40 & 65 & 80 & 105 & 125 \crConfiguration & \multispan7 SPI \strut \crPackage & \multispan7 \hfil 52-Lead (7mm $\times$ 8mm) QFN \hfil \strut \cr}\caption/t The summary of the currently available ADC types and theirs characteristics.\endinsertAll parts in this category are compatible with one board layout. The main differences lay in the sampling frequency and signal to noise ratio, with the slowest having a maximum sampling frequency of 20 MHz. However, all of them have a minimal sampling frequency of 5 MSPS and all are configurable over a serial interface (SPI). SPI seems to be a standard interface used in high-end ADC chips made by the largest manufacturers (Analog Devices, Linear technology, Texas instruments, Maxim integrated..). We have selected two slowest types for our evaluation design. Following that, a PCB for this part have been designed.We have decided that ADCdual01A modules will have a standard MLAB construction layout with four mounting holes in corners aligned in defined raster of 400 mils.Data serial data outputs of ADC modules should be connected directly by LVDS signalling levels conducted by SATA cables to FPGAs for the basic primary signal processing. The ADC chips used in the modules have a selectable bit width of data output bus and thus the output SATA connectors have signals arranged to contain a single bit from every ADC channel. This creates a signal concept enabling a selection of proper bus bit-width according to the sampling rate (higher bus bit-width downgrades signalling speed and vice versa.)In order to connect the above mentioned signalling layout, miniSAS to multiple SATA cable should be used as described in section \ref[signal-cables].A KiCAD design suite had been chosen for PCB layout. However, the version, despite having integrated CERN Push \& Shove routing capability, is slightly unstable as it sometimes crushes due to an exception during routing. On the basis of these stability issues, the design had to be saved quite often. On the other hand, compared to commercially available solutions, such as MentorGraphics PADS or Cadence Orcad, the Open-source KiCAD provides an acceptable option and it easily surpasses a widely used Eagle software.As a part of work on the thesis, new PCB footprints for FMC, SATA, ADCs a and miniSAS connectors have been designed and were committed to KiCAD github library repository. They are now publicly available on the official KiCAD repository at GitHub.ADCdual01A module has several digital data output formats. Difference between these modes lays in the number of differential pairs used.\begitems* 1-lane mode* 2-lane mode* 4-lane mode\enditemsAll of the above-mentioned modes are supported by the module design. For the discussed data acquisition system, the 1-lane mode was selected. 1-lane mode allows a minimal number of differential pairs between ADCdual01A and FPGA. Digital signalling scheme used in 1-lane mode is shown in the following image \ref[1-line-out].\midinsert\clabel[1-line-out]{Single line ADC output signals}\picw=15cm \cinspic ./img/ADC_single_line_output.png\caption/f Digital signalling schema for 1-line ADC digital output mode.\endinsertADCdual01A parameters can be set either by jumper setup (referred to as a parallel programming in the device's data sheet) or by SPI interface. SPI interface has been chosen for our system, because of the parallel programming's lack of options (test pattern output setup for example).Complete schematic diagram of ADCdual01A module board is included in the appendix.\secc ADC modules interface\midinsert\picw=10cm \cinspic ./img/FMC2DIFF_Top_Big.JPG\picw=10cm \cinspic ./img/FMC2DIFF_Bottom_Big.JPG\caption/f Realised PCB of FMC2DIFF01A module.\endinsertBoth of the ADCdual01A modules were connected to FPGA ML605 board trough FMC2DIFF01A adapter board. The design of this adapter expects the presence of FMC LPC connector on host side and the board is, at the same time, not compatible with MLAB. It is, on the other hand, designed to meet the VITA 57 standard specifications for boards which support region 1 and region 3. VITA 57 regions are explained in the picture \ref[VITA57-regions].This industry standard guarantees the compatibility with other FPGA boards that have FMC LPC connectors for Mezzanine Card. Schematic diagram of designed adapter board is included in the appendix.The primary purpose of the PCB is to enable the connection of ADC modules located outside the PC case with ML605 development board. (In PC box analog circuits cannot be realized without the use of massive RFI mitigation techniques).Differential signalling connectors should be used for conducting digital signal over relatively long cables. The signal integrity sensitive links (clocks) are equipped with output driver and translator to LVPECL logic for better signal transmission quality.LVPECL level signal connectors on FMC2DIFF01A board are dedicated to transmit the clock signals. We have selected the SY55855V and SY55857L dual translators. Dual configuration in useful due to fact, that SATA cable contains two differential pairs.The SY55855V is a fully differential, CML/PECL/LVPECL-to-LVDS translator. It achieves LVDS signalling up to 1.5Gbps, depending on the distance and the characteristics of the media and noise coupling sources.LVDS is intended to drive 50 $\Omega$ impedance transmission line media such as PCB traces, backplanes, or cables. SY55855V inputs can be terminated with a single resistor between the true and the complement pins of a given input \cite[SY55855V-chip].The SY55857L is a fully differential, high-speed dual translator optimized to accept any logic standard from single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements\cite[SY55857L-chip].Inputs of both used chips are terminated accordingly to used logic. The LVDS input is terminated differentially by 100 $\Omega$ resistor between positive and negative inputs. PECL input is terminated by Thevenin resistor network. Thevenin termination method was selected as optimal one, due to the absence of a proper power voltage (1,3 V) for direct termination by 50 $\Omega$ resistors. Termination on FPGA side is realized directly by settings the proper digital logic type on input pins.\midinsert\clabel[ML605-development-board]{ML605 development board}\picw=10cm \cinspic ./img/ML605-board.jpg\caption/f FPGA ML605 development board.\endinsert\midinsert\clabel[VITA57-regions]{VITA57 board geometry}\picw=10cm \cinspic ./img/VITA57_regions.png\caption/f Definition of VITA57 regions.\endinsert% doplnit presny pocet konektoruSeveral SATA connectors and two miniSAS connectors are populated on this board. This set of connectors allows a connection of any number of ADC modules within the range of 1 to 8. ADC data outputs should be connected to the miniSAS connectors, while other supporting signals should be routed directly to SATA connectors on adapter.Lengths of differential pairs routed on PCB of the module are not matched between the pairs. Length variation of differential pairs is not critical in our design according to facts discussed in paragraph \ref[diff-signaling]. Nevertheless, signals within differential pairs themselves are matched for length. Internal signal trace length matching of differential pairs is mandatory in order to minimize jitter and avoid a dynamic logic hazard conditions on digital signals in worst case. Thus clocks signals are routed in the most precise way on all designed boards.Signal configuration used in our trial design is described in the following tables \ref[minisas-interface], \ref[SPI-system] and \ref[clock-interconnections].\midinsert \clabel[minisas-interface]{miniSAS differential pairs connections}\ctable {cccc}{miniSAS & SATA pair & FMC signal & Used as \crP0 & 1 & LA03 & not used \crP0 & 2 & LA04 & not used \crP1 & 1 & LA08 & not used \crP1 & 2 & LA07 & not used \crP2 & 1 & LA16 & ADC1 CH1 (LTC2190) \crP2 & 2 & LA11 & ADC1 CH2 (LTC2190) \crP3 & 1 & LA17 & ADC2 CH1 (LTC2271) \crP3 & 2 & LA15 & ADC2 CH2 (LTC2271) \cr}\caption/t miniSAS (FMC2DIFF01A J7) signal connections between modules.\endinsert\midinsert \clabel[SPI-system]{SPI configuration interface connections}\ctable {ccc}{SPI connection J7 & FMC signal & Connected to \crSAS-AUX1 & LA14\_N & SPI DOUT \crSAS-AUX2 & LA14\_P & SPI CLK \crSAS-AUX3 & LA12\_N & CE ADC1 \crSAS-AUX4 & LA12\_P & CE ADC2 \crSAS-AUX5 & LA13\_N & soldered to GND \crSAS-AUX6 & LA13\_P & not used \crSAS-AUX7 & LA09\_N & not used \crSAS-AUX8 & LA09\_P & soldered to GND \cr}\caption/t SPI system interconnections\endinsertSPI interface is used in an unusual way in this design. SPI Data outputs from ADCs are not connected anywhere and read back is not possible, thus the configuration written to registers in ADC module cannot be validated. We have not observed any problems with this system, but it may be a possible source of failures.\midinsert \clabel[clock-interconnections]{System clock interconnections}\ctable {lccc}{Signal & FMC signal & FMC2DIFF01A & ADCdual01A \crDCO & CLK1\_M2C & J5-1 & J13-1 \crFR & LA18\_CC & J10-1 & J12-1 \crENC & LA01\_CC & J2-1(PECL OUT) & J3-1 \crSDGPSDO01A LO & CLK0\_M2C & J3-1 (PECL IN) & N/A \cr}\caption/t Clock system interconnections\endinsert\secc FPGA functionSeveral tasks in separate FPGA blocks are performed by FPGA. In first block FPGA prepares sampling clock for ADCdual01A modules by division of main local oscillator. This task is separate block in FPGA and runs asynchronously to other logical circuits. Second block is SPI configuration module, which sends configuration words to ADC modules it is activated by opening of Xillybus interface file. Third block represents the main module, which resolves ADC - PC communication itself it communicates via PCIe, collect data from ADC hardware and creates data packet \ref[xillybus-interface]. Last block is activated after ADC configuration via SPI.Communication over PCIe is managed by proprietary IP Core and Xillybus driver, which transfers data from FPGA registers to host PC. Data appear in system device file named "/dev/xillybus_data2_r" on the host computer. Binary data which appear in this file after its opening are described in the table below \ref[xillybus-interface].\midinsert\def\tabiteml{ }\let\tabitemr=\tabiteml\clabel[xillybus-interface]{Grabber binary output format}\ctable {lccccccccc}{\hfil & \multispan9 \hfil 160bit packet \hfil \strut \crl \tskip4ptData name & FRAME & \multispan2 \hfil ADC1 CH1 \hfil & \multispan2 \hfil ADC1 CH2 \hfil & \multispan2 \hfil ADC2 CH1 \hfil & \multispan2 \hfil ADC2 CH2 \hfil \strut \crData type & uint32 & int16 & int16 & int16 & int16 & int16 & int16 & int16 & int16 \crContent & saw signal & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ & $t1$ & $t_{1+1}$ \cr}\caption/t System device "/dev/xillybus_data2_r" data format\endinsertData packet block which is carried on PCI Express is described by table \ref[xillybus-interface]. The data packet consist several 32bit words. First word contain FRAME number and it is filled by saw signal for now, with increment step of every data packet transmission. Following data words contains samples from ADCs for first and second channel. Samples from every channel is transmitted in pairs of two samples. Number of ADC channels is expandable according to number of physically connected channels. An CRC word may be added in future at end of transmission packet for data integrity validation.FRAME word at beginning of data packet now filled with incrementing and overflowing saw signal is used for ensure that no data samples ale lost during data transfers from FPGA. FRAME signal may be used in future for pairing the ADC samples data packet with another data packet in future. This new additional data packet should carry meta-data information about sample time jitter, current accuracy of local oscillator frequency etc.Detailed description of currently implemented FPGA functions can be found in separate paper \cite[fpga-middleware]. HDL source codes for FPGA at state which was used are included on enclosed CD. Future development versions are publicly available from MLAB sources repository.% doplnit odkaz na mlab repozitar\secc Data reading and recordingIn order to read the data stream from the ADC drive, we use Gnuradio software. Gnuradio suite consists of gnuradio-companion package which is a graphical tool for creating signal-flow graphs and generating Python flow-graph source code. This tool was used to create a basic RAW data grabber to record and interactively view waterfall plots the data streams output from ADC modules.\midinsert\clabel[grabber-flow-graph]{Gnuradio flow graph for signal grabbing}\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/screenshots/Grabber.grc.png }\par\nobreak \vskip\wd0 \vskip-\ht0\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}\caption/f The ADC recorder flow graph created in gnuradio-companion.\endinsert\midinsert\picw=15cm \cinspic ./img/screenshots/Grabber_running.png\caption/f User interface window of a running ADC grabber.\endinsertThe interactive grabber-viewer user interface shows live oscilloscope-like time-value display for all data channels and live time-frequency scrolling display (a waterfall view) for displaying the frequency components of the grabbed signal. Signal is grabbed to file with exactly the same format, as it is described in table \ref[xillybus-interface].\chap Achieved parametersTrial design construction was tested for proper handling of sampling rates in range of 5 MSPS to 15 MSPS it should work above this limit. System works on i7 8 cores computer with Ubuntu 12.04 LTS operating system. Data recording of input signal is impossible above sampling rates around 7 MSPS due to bottleneck at HDD speed limits, it should be resolved by use of SSD disk drive. But it is not tested in our setup.\sec Measured parametersTwo prototypes of ADC modules were assembled and tested. The first prototype, labeled ADC1, has LTC2190 ADC chip populated with LT6600-5 front-end operational amplifier. It also has a 1kOhm resistors populated on inputs which give it an ability of an internal attenuation of the input signal. The value of this attenuation $A$ is described by the following formula \ref[ADC1-gain]\label[ADC1-gain]$$A = {806 \cdot R_1 \over R_1 + R_2} \eqmark$$Where the letters stand for:\begitems* $A$ - Gain of an input amplifier.* $R_1$ - Output impedance of signal source (usually 50 Ohm).* $R_2$ - Value of serial resistors at operational amplifier inputs.\enditemsWe have $R_2 = 1000 \Omega$ and $R_1 = 50 \Omega$ which imply that $A = 0.815$. That value of A is further confirmed by the measurement.In our measurement setup we have H1012 Ethernet transformer connected to inputs of ADC. We have used this transformer for signal symetrization from BNC connector at Agilent 33220A signal generator. Circuit diagram of used transformer circuit is shown in picture \ref[balun-circuit] and circuit realization in photograph \ref[SMA2SATA-nest].\midinsert\clabel[balun-circuit]{Balun transformer circuit}\picw=10cm \cinspic ./img/SMA2SATA.pdf\caption/f Simplified balun transformer circuit diagram.\endinsertThe signal generator Agilent 33220A which we used does not have optimal parameters for this type of dynamic range measurement. Signal distortion and spurious levels are only -70 dBc according to Agilent datasheet \cite[33220A-generator]. We have managed to measure an ADC saturation voltage of 705.7 mV (generator output) with this setup, mostly due to an impedance mismatch and uncalibrated measurement setup, with 1V ADC range selected by sense pin. This is a relatively large error, but the main result of our measurement, seen as a FFT plot shown in image \ref[ADC1-FFT], confirms $>$80 dB dynamic range at ADC module input.\midinsert\clabel[ADC1-FFT]{ADC1 sine test FFT}\picw=15cm \cinspic ./img/screenshots/ADC1_CH2_FFT.png\caption/f Sine signal sampled by ADC1 module with LTC2190 and LT6600-5 devices.\endinsertSimilar test was performed at ADC2 module. For ADC2 we have to use formula with a different constant \ref[ADC1-gain]. The ADC2 module has LT6600-2.5 amplifiers populated on it with gain equal to $A = 2.457$ and uses the same $R_2$ resistors. We measured saturation voltage of 380 mV (generator output) at channel 1 on this ADC. It is well in parameter tolerances of used setup.\label[ADC2-gain]$$A = {1580 \cdot R_1 \over R_1 + R_2} \eqmark$$Where the letters stand for:\begitems* $A$ - Gain of an input amplifier.* $R_1$ - Output impedance of signal source (usually 50 Ohm).* $R_2$ - Value of serial resistors at operational amplifier inputs.\enditems\midinsert\clabel[ADC2-FFT]{ADC2 sine test FFT}\picw=15cm \cinspic ./img/screenshots/ADC2_CH1_FFT.png\caption/f Sine signal sampled by ADC2 module with LTC2271 and LT6600-2.5 devices.\endinsertComputed FFT spectra for measured signal are shown in the images \ref[ADC2-FFT] and \ref[ADC1-FFT]. Both images confirm that ADCdual01A modules have input dynamical range of 80 dB at least.\midinsert\clabel[SMA2SATA-nest]{Used balun transformer}\picw=15cm \cinspic ./img/SMA2SATA_nest1.JPG\caption/f Balun transformer circuit used for ADC parameters measurement. It is constructed from H1012 transformer salvaged from an old Ethernet card.\endinsert\sec Example of usageFor additional validation of system characteristics a receiver setup has been constructed.\secc Basic interferometric stationInterferometry station was chosen to serve as the most basic experimental setup. We connected the new data acquisition system to two SDRX01B receivers. Block schematics of the setup used is shown in image \ref[block-schematic]. Two ground-plane antennae were used and mounted outside the balcony at CTU building at location 50$^\circ$ 4' 36.102'' N, 14$^\circ$ 25' 4.170'' E.Antennae were equipped by LNA01A amplifiers. All coaxial cables have the same length of 5 meters. Antennae were isolated by common mode ferrite bead mounted on cable to minimise the signal coupling between antennas. Evaluation system consists of SDGPSDO local oscillator subsystem used to tune the local oscillator frequency.\midinsert\clabel[block-schematic]{Receiver block schematic}\picw=\pdfpagewidth \setbox0=\hbox{\inspic ./img/Basic_interferometer.png }\par\nobreak \vskip\wd0 \vskip-\ht0\centerline {\kern\ht0 \pdfsave\pdfrotate{90}\rlap{\box0}\pdfrestore}\caption/f Complete receiver block schematic of dual antenna interferometric station.\endinsert% doplnit schema skutecne pouziteho systemuDespite of the schematic diagram proposed at beginning of system description....We used two separate oscillators -- one oscillator drives encode signal to ADCs still through FPGA based divider and other one drives SDRX01B mixer.The reason for this modification is a simplification of frequency tuning during the experiment. It is because a single oscillator may be used only with a proper setting of FPGA divider and this divider may be modified only by recompilation of FPGA code and loading/flashing a new FPGA schema. Due to fact that the FPGA is connected to PCI express and kernel drivers with hardware must be reinitialized, reboot of PC is required every time a FPGA scheme is changed. Instead of this complicated procedure, we set the FPGA divider to a constant division factor of 30 and used another district oscillator for ADCdual01 sampling modules and for SDRX01B receiver.We use ACOUNT02A MLAB instrument for frequency checking of correct setup on both local oscillators.\midinsert\clabel[meteor-reflection]{Meteor reflection}\picw=10cm \cinspic ./img/screenshots/observed_meteor.png\caption/f Meteor reflection received by evaluation setup.\endinsert\midinsert\clabel[phase-difference]{Phase difference}\picw=10cm \cinspic ./img/screenshots/phase_difference.png\caption/f Demonstration of phase difference between antennae.\endinsertFor the simplest demonstration of phase difference between antennae, we have analysed part of the signal by complex conjugate multiplication between channels. Results of this analysis can be seen in the following picture \ref[phase-difference]. Points of the selected part of signal create a clear vector, which illustrates the presence of the phase difference.\secc Simple passive Doppler radar% doplnit popis\secc Simple polarimeter station% doplnit popis\chap Proposition of the final systemThe construction of a final system, that is supposed to be employed for real radioastronomy observations will be described in this chapter. It is mainly a theoretical analysis of the data handling systems. Realization of the described ideas might be possible as a part of our future development after we fully evaluate and test the current trial design.The system requires proper handling of huge amounts of data and either huge and fast storage capacity is needed for store captured signal data, or enormous computational power is required for online data processing and filtering. Several hardware approach currently exist and are in use for data processing problem handling. Either powerful multi gigahertz CPUs, GPUs, FPGAs, or specially constructed ASICs are used for this task.\sec Custom design of FPGA boardIn the beginning of the project, a custom design of FPGA interface board had been considered. This FPGA board should include PCI express interface and should sell at lower price than the trial design. It should be compatible with MLAB internal standards which is further backward compatible with the existing or improved design of ADC modules. For a connection of FPGA board to another adapter board with PCIe we expect a use of a PCIe host interface.Thunderbolt technology standard was expected to be used in this PC to PCIe module which further communicate with MLAB compatible FPGA module. Thunderbolt chips are currently available on the market for reasonable prices \cite[thunderbolt-chips]. However, a problem lies in the accessibility to their specifications, as specification is only available for licensed users and Intel has a mass market oriented licensing policy, that makes this technology inaccessible for low quantity production. As a consequence, an external PCI Express cabling and expansion slots should be considered as a better solution, if we need preserve standard PC as main computational platform.However, these PCI express external systems and cables are still very expensive. Take Opal Kelly XEM6110 \cite[fpga-pcie] as an example, with its price tag reaching 995 USD at time of writing of thesis.Therefore, a better solution probably needs to be found.An interface problem will by probably resolved by other than Intel ix86 architecture. Many ARM computers have risen on market due to an increased demand of embedded technologies, which require high computation capacity, low power consumption and small size -- especially smartphones. Many of those ARM based systems have interesting parameters of signal processing. These facts make Intel's ix86 architecture unattractive for future projects.\sec Parralella board computerParallella is a new product created by Adapteva, Inc. \cite[parallella-board]. It represents a small supercomputer, that has been in development for almost two years with only testing series of boards produced until now (first single-board computers with 16-core Epiphany chip were shipped in December 2013) \cite[parallella-board]. The board has nearly ideal parameters for signal processing (as it provides around 50 GFLOPS of computational power). It is is equipped with Epiphany coprocessor which has 16 High Performance RISC CPU Cores, Zynq-7020 FPGA with Dual ARM® Cortex™-A9 MPCore™ and operating frequency of 866 MHz, 1GB RAM, 85K Logic Cells, 10/100/1000 Ethernet and OpenCL support \cite[parallella16-board]. In addition to this, the board consumes only 3 Watts of power if both Zynq and Epiphany cores are running simultaniously.The main disadvantage of Parralella board is its unknown lead time and an absence of SATA interface or other interface suitable for data storage connection. Fast data storage interface would be useful and would allow bulk processing of captured data. Following that, the results of data processing may be sent over the Ethernet interface to data storage server.\midinsert\clabel[img-parallella-board]{Parallella board overview}\picw=15cm \cinspic ./img/ParallellaTopView31.png\caption/f Top view on Parallella-16 board \cite[parallella16-board].\endinsertIf Parallella board will be used as a radioastronomy data interface, there would be a demand for new ADC interface module. The interface module will use four PEC connectors mounted on the bottom of the Parallella board. This daughter module should have MLAB compatible design and should preferably be constructed as separable modules for every Parallella's PEC connectors.\sec GPU based computational systemA new GPU development board NVIDIA K1, shown in the following picture \ref[img-NVIDIA-K1], has recently been released. These boards are intended to be used in fields including computer vision, robotics, medicine, security or automotive industry. They have good parameters for signal processing for a relatively low price of 192 USD. Unfortunately, they are currently only in pre-order release stage (in April 2014).\midinsert\clabel[img-NVIDIA-K1]{NVIDIA Jetson TK1 Development Kit}\picw=15cm \cinspic ./img/Jetson_TK1_575px.jpg\caption/f The NVIDIA Jetson TK1 Development Kit \cite[nvidia-k1].\endinsertNVIDIA board differs from other boards in its category by a presence of PCI Experess connector. If we decide to use this development board in our radio astronomy digitalisation system, the PCI express should be used for FPGA connection. A new FPGA board with PCI Express direct PCB connector% doplnit popis pripojeni FPGA desky s HDMI Kabelem.\sec Other ARM based computation systemsOther embedded ARM based computers, for example ODROID-XU, lack a suitable high speed interface. Their highest speed interface is USB 3.0 which has currently unsettled development support and needs commercial software tools for evaluation and testing.From the summary analysis mentioned above, the Parrallella board should be a best candidate for computational board in radioastronomy data acquisition system, as it is optimised for high data flow processing. On one hand, Parrallella does not have much memory to cache the processing data but on the other hand it has wide bandwidth data channels instead. Other boards might provide much more computational power -- 300 GFLOPS in case of NVIDIA K1, but they are optimised for heavy computational tasks on limited amount of data which represents a typical problem in computer graphics. However, in our application we do not need such extreme computation power at data acquisition system level.As a result we should presumably wait until Parallella becomes widely available. Following that, a new ADCdual interface board should be designed and prepared to be used in new scalable radio astronomy data acquisition system. In the meantime, before suitable computing hardware become accessible, the required applications and algorithms should be optimised using the proposed trial design. with FPGA development board on standard PC host computer with PCI Express interface to development board.