?lang_form?
?lang_select?
?lang_submit?
?lang_endform?
{HEADER END}
{FILE START}
library
?curdirlinks? - Rev 3
?prevdifflink? - Blame - ?getfile?
#nolist
//
// Komplete definition of all Special Feature Registers for CCS C compiler
//
// PIC16F873
// PIC16F874
// PIC16F876
// PIC16F877
//
// (c)miho 2005
//
// History:
//
// 1.00 First Version, not verified yet
// SFR Registers in Memory Bank 0
//
#byte INDF = 0x00
#byte TMR0 = 0x01
#byte PCL = 0x02
#byte STATUS = 0x03
#bit IRP = STATUS.7
#bit RP1 = STATUS.6
#bit RP0 = STATUS.5
#bit TO = STATUS.4
#bit PD = STATUS.3
#bit Z = STATUS.2
#bit DC = STATUS.1
#bit C = STATUS.0
#byte FSR = 0x04
#byte PORTA = 0x05
#byte PORTB = 0x06
#byte PORTC = 0x07
#byte PORTD = 0x08
#byte PORTE = 0x09
#byte PCLATH = 0x0A
#byte INTCON = 0x0B
#bit GIE = INTCON.7
#bit PEIE = INTCON.6
#bit T0IE = INTCON.5
#bit INTE = INTCON.4
#bit RBIE = INTCON.3
#bit T0IF = INTCON.2
#bit INTF = INTCON.1
#bit RBIF = INTCON.0
#byte PIR1 = 0x0C
#bit PSPIF = PIR1.7
#bit ADIF = PIR1.6
#bit RCIF = PIR1.5
#bit TXIF = PIR1.4
#bit SSPIF = PIR1.3
#bit CCP1IF = PIR1.2
#bit TMR2IF = PIR1.1
#bit TMR1IF = PIR1.0
#byte PIR2 = 0x0D
#bit EEIF = PIR2.4
#bit BCLIF = PIR2.3
#bit CCP2IF = PIR2.0
#byte TMR1L = 0x0E
#byte TMR1H = 0x0F
#byte T1CON = 0x10
#bit T1CKPS1 = T1CON.5
#bit T1CKPS0 = T1CON.4
#bit T1OSCEN = T1CON.3
#bit T1SYNC = T1CON.2
#bit TMR1CS = T1CON.1
#bit TMR1ON = T1CON.0
#byte TMR2 = 0x11
#byte T2CON = 0x12
#bit TOUTPS3 = T2CON.6
#bit TOUTPS2 = T2CON.5
#bit TOUTPS1 = T2CON.4
#bit TOUTPS0 = T2CON.3
#bit TMR2ON = T2CON.2
#bit T2CKPS1 = T2CON.1
#bit T2CKPS0 = T2CON.0
#byte SSPBUF = 0x13
#byte SSPCON = 0x14
#bit WCOL = SSPCON.7
#bit SSPOV = SSPCON.6
#bit SSPEN = SSPCON.5
#bit CKP = SSPCON.4
#bit SSPM3 = SSPCON.3
#bit SSPM2 = SSPCON.2
#bit SSPM1 = SSPCON.1
#bit SSPM0 = SSPCON.0
#byte CCPR1L = 0x15
#byte CCPR1H = 0x16
#byte CCP1CON = 0x17
#bit CCP1X = CCP1CON.5
#bit CCP1Y = CCP1CON.4
#bit CCP1M3 = CCP1CON.3
#bit CCP1M2 = CCP1CON.2
#bit CCP1M1 = CCP1CON.1
#bit CCP1M0 = CCP1CON.0
#byte RCSTA = 0x18
#bit SPEN = RCSTA.7
#bit RX9 = RCSTA.6
#bit SREN = RCSTA.5
#bit CREN = RCSTA.4
#bit ADDEN = RCSTA.3
#bit FERR = RCSTA.2
#bit OERR = RCSTA.1
#bit RX9D = RCSTA.0
#byte TXREG = 0x19
#byte RCREG = 0x1A
#byte CCPR2L = 0x1B
#byte CCPR2H = 0x1C
#byte CCP2CON = 0x1D
#bit CCP2X = CCP2CON.5
#bit CCP2Y = CCP2CON.4
#bit CCP2M3 = CCP2CON.3
#bit CCP2M2 = CCP2CON.2
#bit CCP2M1 = CCP2CON.1
#bit CCP2M0 = CCP2CON.0
#byte ADRESH = 0x1E
#byte ADCON0 = 0x1F
#bit ADCS1 = ADCON0.7
#bit ADCS0 = ADCON0.6
#bit CHS2 = ADCON0.5
#bit CHS1 = ADCON0.4
#bit CHS0 = ADCON0.3
#bit GO = ADCON0.2
#bit ADON = ADCON0.0
// SFR Registers in Memory Bank 1
//
#byte INDF_1 = 0x80 // miror
#byte OPTION_REG = 0x81
#bit RBPU = OPTION_REG.7
#bit INTEDG = OPTION_REG.6
#bit T0CS = OPTION_REG.5
#bit T0SE = OPTION_REG.4
#bit PSA = OPTION_REG.3
#bit PS2 = OPTION_REG.2
#bit PS1 = OPTION_REG.1
#bit PS0 = OPTION_REG.0
#byte PCL_1 = 0x82 // mirror
#byte STATUS_1 = 0x83 // mirror
#bit IRP_1 = STATUS_1.7
#bit RP1_1 = STATUS_1.6
#bit RP0_1 = STATUS_1.5
#bit TO_1 = STATUS_1.4
#bit PD_1 = STATUS_1.3
#bit Z_1 = STATUS_1.2
#bit DC_1 = STATUS_1.1
#bit C_1 = STATUS_1.0
#byte FSR_1 = 0x84 // mirror
#byte TRISA = 0x85
#byte TRISB = 0x86
#byte TRISC = 0x87
#byte TRISD = 0x88
#byte TRISE = 0x89
#bit IBF = TRISE.7
#bit OBF = TRISE.6
#bit IBOV = TRISE.5
#bit PSPMODE = TRISE.4
#byte PCLATH_1 = 0x8A // mirror
#byte INTCON_1 = 0x8B // mirror
#bit GIE_1 = INTCON_1.7
#bit PEIE_1 = INTCON_1.6
#bit TMR0IE_1 = INTCON_1.5
#bit INTE_1 = INTCON_1.4
#bit RBIE_1 = INTCON_1.3
#bit T0IF_1 = INTCON_1.2
#bit INTF_1 = INTCON_1.1
#bit RBIF_1 = INTCON_1.0
#byte PIE1 = 0x8C
#bit PSPIE = PIE1.7
#bit ADIE = PIE1.6
#bit RCIE = PIE1.5
#bit TXIE = PIE1.4
#bit SSPIE = PIE1.3
#bit CCP1IE = PIE1.2
#bit TMR2IE = PIE1.1
#bit TMR1IE = PIE1.0
#byte PIE2 = 0x8D
#bit EEIE = PIE2.4
#bit BCLIE = PIE2.3
#bit CCP2IE = PIE2.0
#byte PCON = 0x8E
#bit POR = PCON.1
#bit BOR = PCON.0
#byte SSPCON2 = 0x91
#bit GCEN = SSPCON2.7
#bit ACKSTAT = SSPCON2.6
#bit ACKDT = SSPCON2.5
#bit ACKEN = SSPCON2.4
#bit RCEN = SSPCON2.3
#bit PEN = SSPCON2.2
#bit RSEN = SSPCON2.1
#bit SEN = SSPCON2.0
#byte PR2 = 0x92
#byte SSPADD = 0x93
#byte SSPSTAT = 0x94
#bit SMP = SSPSTAT.7
#bit CKE = SSPSTAT.6
#bit DA = SSPSTAT.5
#bit P = SSPSTAT.4
#bit S = SSPSTAT.3
#bit RW = SSPSTAT.2
#bit UA = SSPSTAT.1
#bit BF = SSPSTAT.0
#byte TXSTA = 0x98
#bit CSRC = TXSTA.7
#bit TX9 = TXSTA.6
#bit TXEN = TXSTA.5
#bit SYNC = TXSTA.4
#bit BRGH = TXSTA.2
#bit TRMT = TXSTA.1
#bit TX9D = TXSTA.0
#byte SPBRG = 0x99
#byte ADRESL = 0x9E
#byte ADCON1 = 0x9F
#bit ADFM = ADCON1.7
#bit PCFG3 = ADCON1.3
#bit PCFG2 = ADCON1.2
#bit PCFG1 = ADCON1.1
#bit PCFG0 = ADCON1.0
// SFR Registers in Memory Bank 2
//
#byte INDF_2 = 0x100 // mirror
#byte TMR0_2 = 0x101 // mirror
#byte PCL_2 = 0x102 // mirror
#byte STATUS_2 = 0x103 // mirror
#bit IRP_2 = STATUS_2.7
#bit RP1_2 = STATUS_2.6
#bit RP0_2 = STATUS_2.5
#bit TO_2 = STATUS_2.4
#bit PD_2 = STATUS_2.3
#bit Z_2 = STATUS_2.2
#bit DC_2 = STATUS_2.1
#bit C_2 = STATUS_2.0
#byte FSR_2 = 0x104 // mirror
#byte PORTB_2 = 0x106 // mirror
#byte PCLATH_2 = 0x10A // mirror
#byte INTCON_2 = 0x10B // mirror
#bit GIE_2 = INTCON_2.7
#bit PEIE_2 = INTCON_2.6
#bit T0IE_2 = INTCON_2.5
#bit INTE_2 = INTCON_2.4
#bit RBIE_2 = INTCON_2.3
#bit T0IF_2 = INTCON_2.2
#bit INTF_2 = INTCON_2.1
#bit RBIF_2 = INTCON_2.0
#byte EEDATA = 0x10C
#byte EEADR = 0x10D
#byte EEDATH = 0x10E
#byte EEADRH = 0x10F
// SFR Registers in Memory Bank 3
//
#byte INDF_3 = 0x180 // mirror
#byte OPTION_REG_3 = 0x181 // mirror
#bit RBPU_3 = OPTION_REG_3.7
#bit INTEDG_3 = OPTION_REG_3.6
#bit T0CS_3 = OPTION_REG_3.5
#bit T0SE_3 = OPTION_REG_3.4
#bit PSA_3 = OPTION_REG_3.3
#bit PS2_3 = OPTION_REG_3.2
#bit PS1_3 = OPTION_REG_3.1
#bit PS0_3 = OPTION_REG_3.0
#byte PCL_3 = 0x182 // mirror
#byte STATUS_3 = 0x183 // mirror
#bit IRP_3 = STATUS_3.7
#bit RP1_3 = STATUS_3.6
#bit RP0_3 = STATUS_3.5
#bit TO_3 = STATUS_3.4
#bit PD_3 = STATUS_3.3
#bit Z_3 = STATUS_3.2
#bit DC_3 = STATUS_3.1
#bit C_3 = STATUS_3.0
#byte FSR_3 = 0x184 // mirror
#byte TRISB_3 = 0x186 // mirror
#byte PLATH_3 = 0x18A // mirror
#byte INTCON_3 = 0x18B // mirror
#bit GIE_3 = INTCON_3.7
#bit PEIE_3 = INTCON_3.6
#bit T0IE_3 = INTCON_3.5
#bit INTE_3 = INTCON_3.4
#bit RBIE_3 = INTCON_3.3
#bit T0IF_3 = INTCON_3.2
#bit INTF_3 = INTCON_3.1
#bit RBIF_3 = INTCON_3.0
#byte EECON1 = 0x18C
#bit EEPGD = EECON1.7
#bit WRERR = EECON1.3
#bit WREN = EECON1.2
#bit WR = EECON1.1
#bit RD = EECON1.0
#byte EECON2 = 0x18D
#list
|
{FILE END}
{FOOTER START}
Powered by WebSVN v2.8.3