library ieee;
use ieee.std_logic_1164.all;

entity swap_endianness is
  port (
                i_data : in std_logic_vector;
                o_data : out std_logic_vector
        );
                
end swap_endianness;

architecture behavioral of swap_endianness is
                
begin

        assert ( i_data'length = o_data'length ) report "The input and output data lengths have to match." severity failure;
        assert ( i_data'length mod 8 = 0 ) report "The data length has to be divisible by 8. (Whole bytes)." severity failure;
        
        swap_gen : for i in 0 to ((i_data'length / 8) - 1) generate
                o_data( 8*(i+1) - 1 downto 8*i ) <= i_data( i_data'length - 8*i - 1 downto i_data'length - 8*(i+1) );   
        end generate;
        
end architecture;