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<!DOCTYPE <h <t <link </head><body> <!-- <div <div <a <h 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 u08 Enc28j60Bank; 00047 u16 NextPacketPtr; 00048 <a 00050 { 00051 00052 } 00053 <a 00055 { 00056 00057 } 00058 <a 00060 { 00061 00062 } 00063 00064 00065 { 00066 00067 00068 00069 00070 00071 00072 00073 00074 } 00075 00076 00077 { 00078 00079 00080 00081 00082 00083 00084 00085 00086 } 00087 <a 00089 { 00090 00091 } 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 00122 <a 00124 { 00125 u08 data; 00126 00127 00128 00129 00130 00131 00132 00133 00134 SPDR = 0x00; 00135 00136 00137 00138 { 00139 SPDR = 0x00; 00140 00141 } 00142 data = SPDR; 00143 00144 00145 00146 00147 00148 } 00149 <a 00151 { 00152 00153 00154 00155 00156 00157 00158 00159 SPDR = data; 00160 00161 00162 00163 00164 } 00165 <a 00167 { 00168 00169 00170 00171 00172 00173 00174 00175 { 00176 00177 SPDR = 0x00; 00178 00179 00180 } 00181 00182 00183 } 00184 <a 00186 { 00187 00188 00189 00190 00191 00192 00193 00194 { 00195 00196 00197 00198 } 00199 00200 00201 } 00202 <a 00204 { 00205 00206 00207 { 00208 00209 00210 00211 00212 } 00213 } 00214 <a 00216 { 00217 00218 00219 00220 00221 } 00222 <a 00224 { 00225 00226 00227 00228 00229 } 00230 <a 00232 { 00233 u16 data; 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 00250 } 00251 <a 00253 { 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 } 00264 <a 00266 { 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 sbi(SPCR, MSTR); 00280 00281 cbi(SPCR, CPOL); 00282 00283 cbi(SPCR,DORD); 00284 00285 cbi(SPCR, SPR0); 00286 cbi(SPCR, SPR1); 00287 00288 00289 sbi(SPCR, SPE); 00290 00291 00292 00293 00294 delay_us(50); 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 } 00384 <a 00386 { 00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 } 00403 <a 00405 { 00406 u16 rxstat; 00407 u16 len; 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 00447 } 00448 <a 00450 { 00451 00452 00453 00454 } 00455 <a 00457 { 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 00468 00469 00470 00471 00472 00473 00474 00475 00476 00477 00478 00479 00480 00481 00482 00483 00484 00485 00486 00487 00488 00489 00490 00491 00492 00493 00494 00495 00496 00497 00498 00499 00500 00501 00502 00503 00504 00505 00506 00507 00508 00509 00510 00511 00512 00513 00514 00515 00516 00517 00518 00519 00520 00521 00522 00523 00524 00525 00526 00527 00528 00529 00530 00531 00532 00533 00534 00535 00536 00537 00538 00539 00540 00541 delay_ms(25); 00542 } 00543 00544 00545 </ <a <img </body> </html>

HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> tml><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"> itle>Procyon AVRlib: net/enc28j60.c Source File</title> href="dox.css" rel="stylesheet" type="text/css"> Generated by Doxygen 1.4.2 --> class="qindex"><a class="qindex" href="main.html">Main Page</a> | <a class="qindex" href="modules.html">Modules</a> | <a class="qindex" href="annotated.html">Data Structures</a> | <a class="qindex" href="dirs.html">Directories</a> | <a class="qindex" href="files.html">File List</a> | <a class="qindex" href="functions.html">Data Fields</a> | <a class="qindex" href="globals.html">Globals</a> | <a class="qindex" href="pages.html">Related Pages</a></div> class="nav"> class="el" href="dir_000001.html">net</a></div> 1>enc28j60.c</h1><a href="enc28j60_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment">00001 /*! \file enc28j60.c \brief Microchip ENC28J60 Ethernet Interface Driver. */ //***************************************************************************** // // File Name : 'enc28j60.c' // Title : Microchip ENC28J60 Ethernet Interface Driver // Author : Pascal Stang (c)2005 // Created : 9/22/2005 // Revised : 9/22/2005 // Version : 0.1 // Target MCU : Atmel AVR series // Editor Tabs : 4 // // Description : This driver provides initialization and transmit/receive // functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. // This chip is novel in that it is a full MAC+PHY interface all in a 28-pin // chip, using an SPI interface to the host processor. // //***************************************************************************** #include "avr/io.h" #include "<a class="code" href="global_8h.html">global.h</a>" #include "<a class="code" href="timer_8h.html">timer.h</a>" #include "<a class="code" href="rprintf_8h.html">rprintf.h</a>" #include "<a class="code" href="enc28j60_8h.html">enc28j60.h</a>" #ifdef SPDR0 #define SPDR SPDR0 #define SPCR SPCR0 #define SPSR SPSR0 #define SPIF SPIF0 #define MSTR MSTR0 #define CPOL CPOL0 #define DORD DORD0 #define SPR0 SPR00 #define SPR1 SPR01 #define SPI2X SPI2X0 #define SPE SPE0 #endif // include configuration #include "<a class="code" href="enc28j60conf_8h.html">enc28j60conf.h</a>" name="l00049"></a><a class="code" href="group__nic.html#ga0">00049</a> void <a class="code" href="group__nic.html#ga0">nicInit</a>(void) <a class="code" href="group__enc28j60.html#ga9">enc28j60Init</a>(); name="l00054"></a><a class="code" href="group__nic.html#ga1">00054</a> void <a class="code" href="group__nic.html#ga1">nicSend</a>(unsigned int len, unsigned char* packet) <a class="code" href="group__enc28j60.html#ga10">enc28j60PacketSend</a>(len, packet); name="l00059"></a><a class="code" href="group__nic.html#ga2">00059</a> unsigned int <a class="code" href="group__nic.html#ga2">nicPoll</a>(unsigned int maxlen, unsigned char* packet) return <a class="code" href="group__enc28j60.html#ga11">enc28j60PacketReceive</a>(maxlen, packet); void nicGetMacAddress(u08* macaddr) // read MAC address registers // NOTE: MAC address in ENC28J60 is byte-backward *macaddr++ = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR5); *macaddr++ = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR4); *macaddr++ = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR3); *macaddr++ = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR2); *macaddr++ = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR1); *macaddr++ = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR0); void nicSetMacAddress(u08* macaddr) // write MAC address // NOTE: MAC address in ENC28J60 is byte-backward <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR5, *macaddr++); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR4, *macaddr++); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR3, *macaddr++); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR2, *macaddr++); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR1, *macaddr++); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR0, *macaddr++); name="l00088"></a><a class="code" href="group__nic.html#ga5">00088</a> void <a class="code" href="group__nic.html#ga5">nicRegDump</a>(void) <a class="code" href="group__enc28j60.html#ga13">enc28j60RegDump</a>(); /* void ax88796SetupPorts(void) { #if NIC_CONNECTION == MEMORY_MAPPED // enable external SRAM interface - no wait states sbi(MCUCR, SRE); // sbi(MCUCR, SRW10); // sbi(XMCRA, SRW00); // sbi(XMCRA, SRW01); // sbi(XMCRA, SRW11); #else // set address port to output AX88796_ADDRESS_DDR = AX88796_ADDRESS_MASK; // set data port to input with pull-ups AX88796_DATA_DDR = 0x00; AX88796_DATA_PORT = 0xFF; // initialize the control port read and write pins to de-asserted sbi( AX88796_CONTROL_PORT, AX88796_CONTROL_READPIN ); sbi( AX88796_CONTROL_PORT, AX88796_CONTROL_WRITEPIN ); // set the read and write pins to output sbi( AX88796_CONTROL_DDR, AX88796_CONTROL_READPIN ); sbi( AX88796_CONTROL_DDR, AX88796_CONTROL_WRITEPIN ); #endif // set reset pin to output sbi( AX88796_RESET_DDR, AX88796_RESET_PIN ); } */ name="l00123"></a><a class="code" href="group__enc28j60.html#ga0">00123</a> u08 <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(u08 <a class="code" href="structnetBootpHeader.html#o0">op</a>, u08 address) // assert CS ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); // issue read command SPDR = op | (address & ADDR_MASK); while(!(SPSR & (1<<SPIF))); // read data while(!(SPSR & (1<<SPIF))); // do dummy read if needed if(address & 0x80) while(!(inb(SPSR) & (1<<SPIF))); // release CS ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); return data; name="l00150"></a><a class="code" href="group__enc28j60.html#ga1">00150</a> void <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(u08 <a class="code" href="structnetBootpHeader.html#o0">op</a>, u08 address, u08 data) // assert CS ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); // issue write command SPDR = op | (address & ADDR_MASK); while(!(SPSR & (1<<SPIF))); // write data while(!(SPSR & (1<<SPIF))); // release CS ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); name="l00166"></a><a class="code" href="group__enc28j60.html#ga2">00166</a> void <a class="code" href="group__enc28j60.html#ga2">enc28j60ReadBuffer</a>(u16 len, u08* data) // assert CS ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); // issue read command SPDR = ENC28J60_READ_BUF_MEM; while(!(SPSR & (1<<SPIF))); while(len--) // read data while(!(SPSR & (1<<SPIF))); *data++ = SPDR; // release CS ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); name="l00185"></a><a class="code" href="group__enc28j60.html#ga3">00185</a> void <a class="code" href="group__enc28j60.html#ga3">enc28j60WriteBuffer</a>(u16 len, u08* data) // assert CS ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); // issue write command SPDR = ENC28J60_WRITE_BUF_MEM; while(!(SPSR & (1<<SPIF))); while(len--) // write data SPDR = *data++; while(!(SPSR & (1<<SPIF))); // release CS ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); name="l00203"></a><a class="code" href="group__enc28j60.html#ga4">00203</a> void <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(u08 address) // set the bank (if needed) if((address & BANK_MASK) != Enc28j60Bank) // set the bank <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0)); <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5); Enc28j60Bank = (address & BANK_MASK); name="l00215"></a><a class="code" href="group__enc28j60.html#ga5">00215</a> u08 <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(u08 address) // set the bank <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(address); // do the read return <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_CTRL_REG, address); name="l00223"></a><a class="code" href="group__enc28j60.html#ga6">00223</a> void <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(u08 address, u08 data) // set the bank <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(address); // do the write <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_WRITE_CTRL_REG, address, data); name="l00231"></a><a class="code" href="group__enc28j60.html#ga7">00231</a> u16 <a class="code" href="group__enc28j60.html#ga7">enc28j60PhyRead</a>(u08 address) // Set the right address and start the register read operation <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIREGADR, address); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MICMD, MICMD_MIIRD); // wait until the PHY read completes while(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MISTAT) & MISTAT_BUSY); // quit reading <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MICMD, 0x00); // get data value data = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MIRDL); data |= <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MIRDH); // return the data return data; name="l00252"></a><a class="code" href="group__enc28j60.html#ga8">00252</a> void <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(u08 address, u16 data) // set the PHY register address <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIREGADR, address); // write the PHY data <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIWRL, data); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIWRH, data>>8); // wait until the PHY write completes while(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MISTAT) & MISTAT_BUSY); name="l00265"></a><a class="code" href="group__enc28j60.html#ga9">00265</a> void <a class="code" href="group__enc28j60.html#ga9">enc28j60Init</a>(void) // initialize I/O sbi(ENC28J60_CONTROL_DDR, ENC28J60_CONTROL_CS); sbi(ENC28J60_CONTROL_PORT, ENC28J60_CONTROL_CS); // setup SPI I/O pins sbi(ENC28J60_SPI_PORT, ENC28J60_SPI_SCK); // set SCK hi sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SCK); // set SCK as output cbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MISO); // set MISO as input sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MOSI); // set MOSI as output sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SS); // SS must be output for Master mode to work // initialize SPI interface // master mode // select clock phase positive-going in middle of data // Data order MSB first // switch to f/4 2X = f/2 bitrate sbi(SPSR, SPI2X); // enable SPI // perform system reset <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); // check CLKRDY bit to see if reset is complete while(!(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ESTAT) & ESTAT_CLKRDY)); // do bank 0 stuff // initialize receive buffer // 16-bit transfers, must write low byte first // set receive buffer start address NextPacketPtr = RXSTART_INIT; <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXSTL, RXSTART_INIT&0xFF); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXSTH, RXSTART_INIT>>8); // set receive pointer address <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTL, RXSTART_INIT&0xFF); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTH, RXSTART_INIT>>8); // set receive buffer end // ERXND defaults to 0x1FFF (end of ram) <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXNDL, RXSTOP_INIT&0xFF); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXNDH, RXSTOP_INIT>>8); // set transmit buffer start // ETXST defaults to 0x0000 (beginnging of ram) <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXSTL, TXSTART_INIT&0xFF); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXSTH, TXSTART_INIT>>8); // do bank 2 stuff // enable MAC receive <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS); // bring MAC out of reset <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MACON2, 0x00); // enable automatic padding and CRC operations <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN); // enc28j60Write(MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN); // set inter-frame gap (non-back-to-back) <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAIPGL, 0x12); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAIPGH, 0x0C); // set inter-frame gap (back-to-back) <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MABBIPG, 0x12); // Set the maximum packet size which the controller will accept <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAMXFLL, MAX_FRAMELEN&0xFF); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAMXFLH, MAX_FRAMELEN>>8); // do bank 3 stuff // write MAC address // NOTE: MAC address in ENC28J60 is byte-backward <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR5, ENC28J60_MAC0); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR4, ENC28J60_MAC1); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR3, ENC28J60_MAC2); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR2, ENC28J60_MAC3); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR1, ENC28J60_MAC4); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR0, ENC28J60_MAC5); // no loopback of transmitted frames <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(PHCON2, PHCON2_HDLDIS); // switch to bank 0 <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(ECON1); // enable interrutps <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE); // enable packet reception <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN); /* enc28j60PhyWrite(PHLCON, 0x0AA2); // setup duplex ---------------------- // Disable receive logic and abort any packets currently being transmitted enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS|ECON1_RXEN); { u16 temp; // Set the PHY to the proper duplex mode temp = enc28j60PhyRead(PHCON1); temp &= ~PHCON1_PDPXMD; enc28j60PhyWrite(PHCON1, temp); // Set the MAC to the proper duplex mode temp = enc28j60Read(MACON3); temp &= ~MACON3_FULDPX; enc28j60Write(MACON3, temp); } // Set the back-to-back inter-packet gap time to IEEE specified // requirements. The meaning of the MABBIPG value changes with the duplex // state, so it must be updated in this function. // In full duplex, 0x15 represents 9.6us; 0x12 is 9.6us in half duplex //enc28j60Write(MABBIPG, DuplexState ? 0x15 : 0x12); // Reenable receive logic enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN); // setup duplex ---------------------- */ name="l00385"></a><a class="code" href="group__enc28j60.html#ga10">00385</a> void <a class="code" href="group__enc28j60.html#ga10">enc28j60PacketSend</a>(unsigned int len, unsigned char* packet) // Set the write pointer to start of transmit buffer area <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(EWRPTL, TXSTART_INIT); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(EWRPTH, TXSTART_INIT>>8); // Set the TXND pointer to correspond to the packet size given <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXNDL, (TXSTART_INIT+len)); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXNDH, (TXSTART_INIT+len)>>8); // write per-packet control byte <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_WRITE_BUF_MEM, 0, 0x00); // copy the packet into the transmit buffer <a class="code" href="group__enc28j60.html#ga3">enc28j60WriteBuffer</a>(len, packet); // send the contents of the transmit buffer onto the network <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS); name="l00404"></a><a class="code" href="group__enc28j60.html#ga11">00404</a> unsigned int <a class="code" href="group__enc28j60.html#ga11">enc28j60PacketReceive</a>(unsigned int maxlen, unsigned char* packet) // check if a packet has been received and buffered // if( !(enc28j60Read(EIR) & EIR_PKTIF) ) if( !<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(EPKTCNT) ) return 0; // Make absolutely certain that any previous packet was discarded //if( WasDiscarded == FALSE) // MACDiscardRx(); // Set the read pointer to the start of the received packet <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERDPTL, (NextPacketPtr)); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERDPTH, (NextPacketPtr)>>8); // read the next packet pointer NextPacketPtr = <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_BUF_MEM, 0); NextPacketPtr |= <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_BUF_MEM, 0)<<8; // read the packet length len = <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_BUF_MEM, 0); len |= <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_BUF_MEM, 0)<<8; // read the receive status rxstat = <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_BUF_MEM, 0); rxstat |= <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_BUF_MEM, 0)<<8; // limit retrieve length // (we reduce the MAC-reported length by 4 to remove the CRC) len = MIN(len, maxlen); // copy the packet from the receive buffer <a class="code" href="group__enc28j60.html#ga2">enc28j60ReadBuffer</a>(len, packet); // Move the RX read pointer to the start of the next received packet // This frees the memory we just read out <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTL, (NextPacketPtr)); <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTH, (NextPacketPtr)>>8); // decrement the packet counter indicate we are done with this packet <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC); return len; name="l00449"></a><a class="code" href="group__enc28j60.html#ga12">00449</a> void <a class="code" href="group__enc28j60.html#ga12">enc28j60ReceiveOverflowRecover</a>(void) // receive buffer overflow handling procedure // recovery completed name="l00456"></a><a class="code" href="group__enc28j60.html#ga13">00456</a> void <a class="code" href="group__enc28j60.html#ga13">enc28j60RegDump</a>(void) // unsigned char macaddr[6]; // result = ax88796Read(TR); // rprintf("Media State: "); // if(!(result & AUTOD)) // rprintf("Autonegotiation\r\n"); // else if(result & RST_B) // rprintf("PHY in Reset \r\n"); // else if(!(result & RST_10B)) // rprintf("10BASE-T \r\n"); // else if(!(result & RST_TXB)) // rprintf("100BASE-T \r\n"); rprintf("RevID: 0x%x\r\n", <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(EREVID)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>("Cntrl: ECON1 ECON2 ESTAT EIR EIE\r\n"); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" "); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ECON1)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" "); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ECON2)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" "); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ESTAT)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" "); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(EIR)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" "); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(EIE)); <a class="code" href="group__rprintf.html#ga5">rprintfCRLF</a>(); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>("MAC : MACON1 MACON2 MACON3 MACON4 MAC-Address\r\n"); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MACON1)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MACON2)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MACON3)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MACON4)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" "); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR5)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR4)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR3)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR2)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR1)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAADR0)); <a class="code" href="group__rprintf.html#ga5">rprintfCRLF</a>(); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>("Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\r\n"); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXSTH)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXSTL)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXNDH)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXNDL)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXWRPTH)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXWRPTL)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXRDPTH)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXRDPTL)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ERXFCON)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(EPKTCNT)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAMXFLH)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAMXFLL)); <a class="code" href="group__rprintf.html#ga5">rprintfCRLF</a>(); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>("Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\r\n"); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ETXSTH)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ETXSTL)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ETXNDH)); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ETXNDL)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MACLCON1)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MACLCON2)); <a class="code" href="group__rprintf.html#ga15">rprintfProgStrM</a>(" 0x"); <a class="code" href="group__rprintf.html#ga7">rprintfu08</a>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MAPHSUP)); <a class="code" href="group__rprintf.html#ga5">rprintfCRLF</a>(); pre></div><hr size="1"><address style="align: right;">Generated on Sun Oct 29 03:41:07 2006 for Procyon AVRlib by  href="http://www.doxygen.org/index.html"> src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.2 </address>

END}