?lang_form?
?lang_select?
?lang_submit?
?lang_endform?
{HEADER END}
{FILE START}
library
?curdirlinks? - Rev 6
?prevdifflink? - Blame - ?getfile?
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>Procyon AVRlib: net/enc28j60.h Source File</title>
<link href="dox.css" rel="stylesheet" type="text/css">
</head><body>
<!-- Generated by Doxygen 1.4.2 -->
<div class="qindex"><a class="qindex" href="main.html">Main Page</a> | <a class="qindex" href="modules.html">Modules</a> | <a class="qindex" href="annotated.html">Data Structures</a> | <a class="qindex" href="dirs.html">Directories</a> | <a class="qindex" href="files.html">File List</a> | <a class="qindex" href="functions.html">Data Fields</a> | <a class="qindex" href="globals.html">Globals</a> | <a class="qindex" href="pages.html">Related Pages</a></div>
<div class="nav">
<a class="el" href="dir_000001.html">net</a></div>
<h1>enc28j60.h</h1><a href="enc28j60_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment">00001 <span class="comment">/*! \file enc28j60.h \brief Microchip ENC28J60 Ethernet Interface Driver. */</span>
00002 <span class="comment">//*****************************************************************************</span>
00003 <span class="comment">//</span>
00004 <span class="comment">// File Name : 'enc28j60.h'</span>
00005 <span class="comment">// Title : Microchip ENC28J60 Ethernet Interface Driver</span>
00006 <span class="comment">// Author : Pascal Stang (c)2005</span>
00007 <span class="comment">// Created : 9/22/2005</span>
00008 <span class="comment">// Revised : 9/22/2005</span>
00009 <span class="comment">// Version : 0.1</span>
00010 <span class="comment">// Target MCU : Atmel AVR series</span>
00011 <span class="comment">// Editor Tabs : 4</span>
00012 <span class="comment">//</span><span class="comment"></span>
00013 <span class="comment">/// \ingroup network</span>
00014 <span class="comment">/// \defgroup enc28j60 Microchip ENC28J60 Ethernet Interface Driver (enc28j60.c)</span>
00015 <span class="comment">/// \code #include "net/enc28j60.h" \endcode</span>
00016 <span class="comment">/// \par Overview</span>
00017 <span class="comment">/// This driver provides initialization and transmit/receive</span>
00018 <span class="comment">/// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.</span>
00019 <span class="comment">/// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin</span>
00020 <span class="comment">/// chip, using an SPI interface to the host processor.</span>
00021 <span class="comment">///</span>
00022 <span class="comment"></span><span class="comment">//</span>
00023 <span class="comment">//*****************************************************************************</span><span class="comment"></span>
00024 <span class="comment">//@{</span>
00025 <span class="comment"></span>
00026 <span class="preprocessor">#ifndef ENC28J60_H</span>
00027 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_H</span>
00028 <span class="preprocessor"></span>
00029 <span class="preprocessor">#include "<a class="code" href="global_8h.html">global.h</a>"</span>
00030
00031 <span class="preprocessor">#define nop() asm volatile ("nop")</span>
00032 <span class="preprocessor"></span>
00033 <span class="comment">// ENC28J60 Control Registers</span>
00034 <span class="comment">// Control register definitions are a combination of address,</span>
00035 <span class="comment">// bank number, and Ethernet/MAC/PHY indicator bits.</span>
00036 <span class="comment">// - Register address (bits 0-4)</span>
00037 <span class="comment">// - Bank number (bits 5-6)</span>
00038 <span class="comment">// - MAC/PHY indicator (bit 7)</span>
00039 <span class="preprocessor">#define ADDR_MASK 0x1F</span>
00040 <span class="preprocessor"></span><span class="preprocessor">#define BANK_MASK 0x60</span>
00041 <span class="preprocessor"></span><span class="preprocessor">#define SPRD_MASK 0x80</span>
00042 <span class="preprocessor"></span><span class="comment">// All-bank registers</span>
00043 <span class="preprocessor">#define EIE 0x1B</span>
00044 <span class="preprocessor"></span><span class="preprocessor">#define EIR 0x1C</span>
00045 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT 0x1D</span>
00046 <span class="preprocessor"></span><span class="preprocessor">#define ECON2 0x1E</span>
00047 <span class="preprocessor"></span><span class="preprocessor">#define ECON1 0x1F</span>
00048 <span class="preprocessor"></span><span class="comment">// Bank 0 registers</span>
00049 <span class="preprocessor">#define ERDPTL (0x00|0x00)</span>
00050 <span class="preprocessor"></span><span class="preprocessor">#define ERDPTH (0x01|0x00)</span>
00051 <span class="preprocessor"></span><span class="preprocessor">#define EWRPTL (0x02|0x00)</span>
00052 <span class="preprocessor"></span><span class="preprocessor">#define EWRPTH (0x03|0x00)</span>
00053 <span class="preprocessor"></span><span class="preprocessor">#define ETXSTL (0x04|0x00)</span>
00054 <span class="preprocessor"></span><span class="preprocessor">#define ETXSTH (0x05|0x00)</span>
00055 <span class="preprocessor"></span><span class="preprocessor">#define ETXNDL (0x06|0x00)</span>
00056 <span class="preprocessor"></span><span class="preprocessor">#define ETXNDH (0x07|0x00)</span>
00057 <span class="preprocessor"></span><span class="preprocessor">#define ERXSTL (0x08|0x00)</span>
00058 <span class="preprocessor"></span><span class="preprocessor">#define ERXSTH (0x09|0x00)</span>
00059 <span class="preprocessor"></span><span class="preprocessor">#define ERXNDL (0x0A|0x00)</span>
00060 <span class="preprocessor"></span><span class="preprocessor">#define ERXNDH (0x0B|0x00)</span>
00061 <span class="preprocessor"></span><span class="preprocessor">#define ERXRDPTL (0x0C|0x00)</span>
00062 <span class="preprocessor"></span><span class="preprocessor">#define ERXRDPTH (0x0D|0x00)</span>
00063 <span class="preprocessor"></span><span class="preprocessor">#define ERXWRPTL (0x0E|0x00)</span>
00064 <span class="preprocessor"></span><span class="preprocessor">#define ERXWRPTH (0x0F|0x00)</span>
00065 <span class="preprocessor"></span><span class="preprocessor">#define EDMASTL (0x10|0x00)</span>
00066 <span class="preprocessor"></span><span class="preprocessor">#define EDMASTH (0x11|0x00)</span>
00067 <span class="preprocessor"></span><span class="preprocessor">#define EDMANDL (0x12|0x00)</span>
00068 <span class="preprocessor"></span><span class="preprocessor">#define EDMANDH (0x13|0x00)</span>
00069 <span class="preprocessor"></span><span class="preprocessor">#define EDMADSTL (0x14|0x00)</span>
00070 <span class="preprocessor"></span><span class="preprocessor">#define EDMADSTH (0x15|0x00)</span>
00071 <span class="preprocessor"></span><span class="preprocessor">#define EDMACSL (0x16|0x00)</span>
00072 <span class="preprocessor"></span><span class="preprocessor">#define EDMACSH (0x17|0x00)</span>
00073 <span class="preprocessor"></span><span class="comment">// Bank 1 registers</span>
00074 <span class="preprocessor">#define EHT0 (0x00|0x20)</span>
00075 <span class="preprocessor"></span><span class="preprocessor">#define EHT1 (0x01|0x20)</span>
00076 <span class="preprocessor"></span><span class="preprocessor">#define EHT2 (0x02|0x20)</span>
00077 <span class="preprocessor"></span><span class="preprocessor">#define EHT3 (0x03|0x20)</span>
00078 <span class="preprocessor"></span><span class="preprocessor">#define EHT4 (0x04|0x20)</span>
00079 <span class="preprocessor"></span><span class="preprocessor">#define EHT5 (0x05|0x20)</span>
00080 <span class="preprocessor"></span><span class="preprocessor">#define EHT6 (0x06|0x20)</span>
00081 <span class="preprocessor"></span><span class="preprocessor">#define EHT7 (0x07|0x20)</span>
00082 <span class="preprocessor"></span><span class="preprocessor">#define EPMM0 (0x08|0x20)</span>
00083 <span class="preprocessor"></span><span class="preprocessor">#define EPMM1 (0x09|0x20)</span>
00084 <span class="preprocessor"></span><span class="preprocessor">#define EPMM2 (0x0A|0x20)</span>
00085 <span class="preprocessor"></span><span class="preprocessor">#define EPMM3 (0x0B|0x20)</span>
00086 <span class="preprocessor"></span><span class="preprocessor">#define EPMM4 (0x0C|0x20)</span>
00087 <span class="preprocessor"></span><span class="preprocessor">#define EPMM5 (0x0D|0x20)</span>
00088 <span class="preprocessor"></span><span class="preprocessor">#define EPMM6 (0x0E|0x20)</span>
00089 <span class="preprocessor"></span><span class="preprocessor">#define EPMM7 (0x0F|0x20)</span>
00090 <span class="preprocessor"></span><span class="preprocessor">#define EPMCSL (0x10|0x20)</span>
00091 <span class="preprocessor"></span><span class="preprocessor">#define EPMCSH (0x11|0x20)</span>
00092 <span class="preprocessor"></span><span class="preprocessor">#define EPMOL (0x14|0x20)</span>
00093 <span class="preprocessor"></span><span class="preprocessor">#define EPMOH (0x15|0x20)</span>
00094 <span class="preprocessor"></span><span class="preprocessor">#define EWOLIE (0x16|0x20)</span>
00095 <span class="preprocessor"></span><span class="preprocessor">#define EWOLIR (0x17|0x20)</span>
00096 <span class="preprocessor"></span><span class="preprocessor">#define ERXFCON (0x18|0x20)</span>
00097 <span class="preprocessor"></span><span class="preprocessor">#define EPKTCNT (0x19|0x20)</span>
00098 <span class="preprocessor"></span><span class="comment">// Bank 2 registers</span>
00099 <span class="preprocessor">#define MACON1 (0x00|0x40|0x80)</span>
00100 <span class="preprocessor"></span><span class="preprocessor">#define MACON2 (0x01|0x40|0x80)</span>
00101 <span class="preprocessor"></span><span class="preprocessor">#define MACON3 (0x02|0x40|0x80)</span>
00102 <span class="preprocessor"></span><span class="preprocessor">#define MACON4 (0x03|0x40|0x80)</span>
00103 <span class="preprocessor"></span><span class="preprocessor">#define MABBIPG (0x04|0x40|0x80)</span>
00104 <span class="preprocessor"></span><span class="preprocessor">#define MAIPGL (0x06|0x40|0x80)</span>
00105 <span class="preprocessor"></span><span class="preprocessor">#define MAIPGH (0x07|0x40|0x80)</span>
00106 <span class="preprocessor"></span><span class="preprocessor">#define MACLCON1 (0x08|0x40|0x80)</span>
00107 <span class="preprocessor"></span><span class="preprocessor">#define MACLCON2 (0x09|0x40|0x80)</span>
00108 <span class="preprocessor"></span><span class="preprocessor">#define MAMXFLL (0x0A|0x40|0x80)</span>
00109 <span class="preprocessor"></span><span class="preprocessor">#define MAMXFLH (0x0B|0x40|0x80)</span>
00110 <span class="preprocessor"></span><span class="preprocessor">#define MAPHSUP (0x0D|0x40|0x80)</span>
00111 <span class="preprocessor"></span><span class="preprocessor">#define MICON (0x11|0x40|0x80)</span>
00112 <span class="preprocessor"></span><span class="preprocessor">#define MICMD (0x12|0x40|0x80)</span>
00113 <span class="preprocessor"></span><span class="preprocessor">#define MIREGADR (0x14|0x40|0x80)</span>
00114 <span class="preprocessor"></span><span class="preprocessor">#define MIWRL (0x16|0x40|0x80)</span>
00115 <span class="preprocessor"></span><span class="preprocessor">#define MIWRH (0x17|0x40|0x80)</span>
00116 <span class="preprocessor"></span><span class="preprocessor">#define MIRDL (0x18|0x40|0x80)</span>
00117 <span class="preprocessor"></span><span class="preprocessor">#define MIRDH (0x19|0x40|0x80)</span>
00118 <span class="preprocessor"></span><span class="comment">// Bank 3 registers</span>
00119 <span class="preprocessor">#define MAADR1 (0x00|0x60|0x80)</span>
00120 <span class="preprocessor"></span><span class="preprocessor">#define MAADR0 (0x01|0x60|0x80)</span>
00121 <span class="preprocessor"></span><span class="preprocessor">#define MAADR3 (0x02|0x60|0x80)</span>
00122 <span class="preprocessor"></span><span class="preprocessor">#define MAADR2 (0x03|0x60|0x80)</span>
00123 <span class="preprocessor"></span><span class="preprocessor">#define MAADR5 (0x04|0x60|0x80)</span>
00124 <span class="preprocessor"></span><span class="preprocessor">#define MAADR4 (0x05|0x60|0x80)</span>
00125 <span class="preprocessor"></span><span class="preprocessor">#define EBSTSD (0x06|0x60)</span>
00126 <span class="preprocessor"></span><span class="preprocessor">#define EBSTCON (0x07|0x60)</span>
00127 <span class="preprocessor"></span><span class="preprocessor">#define EBSTCSL (0x08|0x60)</span>
00128 <span class="preprocessor"></span><span class="preprocessor">#define EBSTCSH (0x09|0x60)</span>
00129 <span class="preprocessor"></span><span class="preprocessor">#define MISTAT (0x0A|0x60|0x80)</span>
00130 <span class="preprocessor"></span><span class="preprocessor">#define EREVID (0x12|0x60)</span>
00131 <span class="preprocessor"></span><span class="preprocessor">#define ECOCON (0x15|0x60)</span>
00132 <span class="preprocessor"></span><span class="preprocessor">#define EFLOCON (0x17|0x60)</span>
00133 <span class="preprocessor"></span><span class="preprocessor">#define EPAUSL (0x18|0x60)</span>
00134 <span class="preprocessor"></span><span class="preprocessor">#define EPAUSH (0x19|0x60)</span>
00135 <span class="preprocessor"></span><span class="comment">// PHY registers</span>
00136 <span class="preprocessor">#define PHCON1 0x00</span>
00137 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1 0x01</span>
00138 <span class="preprocessor"></span><span class="preprocessor">#define PHHID1 0x02</span>
00139 <span class="preprocessor"></span><span class="preprocessor">#define PHHID2 0x03</span>
00140 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2 0x10</span>
00141 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT2 0x11</span>
00142 <span class="preprocessor"></span><span class="preprocessor">#define PHIE 0x12</span>
00143 <span class="preprocessor"></span><span class="preprocessor">#define PHIR 0x13</span>
00144 <span class="preprocessor"></span><span class="preprocessor">#define PHLCON 0x14</span>
00145 <span class="preprocessor"></span>
00146 <span class="comment">// ENC28J60 EIE Register Bit Definitions</span>
00147 <span class="preprocessor">#define EIE_INTIE 0x80</span>
00148 <span class="preprocessor"></span><span class="preprocessor">#define EIE_PKTIE 0x40</span>
00149 <span class="preprocessor"></span><span class="preprocessor">#define EIE_DMAIE 0x20</span>
00150 <span class="preprocessor"></span><span class="preprocessor">#define EIE_LINKIE 0x10</span>
00151 <span class="preprocessor"></span><span class="preprocessor">#define EIE_TXIE 0x08</span>
00152 <span class="preprocessor"></span><span class="preprocessor">#define EIE_WOLIE 0x04</span>
00153 <span class="preprocessor"></span><span class="preprocessor">#define EIE_TXERIE 0x02</span>
00154 <span class="preprocessor"></span><span class="preprocessor">#define EIE_RXERIE 0x01</span>
00155 <span class="preprocessor"></span><span class="comment">// ENC28J60 EIR Register Bit Definitions</span>
00156 <span class="preprocessor">#define EIR_PKTIF 0x40</span>
00157 <span class="preprocessor"></span><span class="preprocessor">#define EIR_DMAIF 0x20</span>
00158 <span class="preprocessor"></span><span class="preprocessor">#define EIR_LINKIF 0x10</span>
00159 <span class="preprocessor"></span><span class="preprocessor">#define EIR_TXIF 0x08</span>
00160 <span class="preprocessor"></span><span class="preprocessor">#define EIR_WOLIF 0x04</span>
00161 <span class="preprocessor"></span><span class="preprocessor">#define EIR_TXERIF 0x02</span>
00162 <span class="preprocessor"></span><span class="preprocessor">#define EIR_RXERIF 0x01</span>
00163 <span class="preprocessor"></span><span class="comment">// ENC28J60 ESTAT Register Bit Definitions</span>
00164 <span class="preprocessor">#define ESTAT_INT 0x80</span>
00165 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_LATECOL 0x10</span>
00166 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_RXBUSY 0x04</span>
00167 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_TXABRT 0x02</span>
00168 <span class="preprocessor"></span><span class="preprocessor">#define ESTAT_CLKRDY 0x01</span>
00169 <span class="preprocessor"></span><span class="comment">// ENC28J60 ECON2 Register Bit Definitions</span>
00170 <span class="preprocessor">#define ECON2_AUTOINC 0x80</span>
00171 <span class="preprocessor"></span><span class="preprocessor">#define ECON2_PKTDEC 0x40</span>
00172 <span class="preprocessor"></span><span class="preprocessor">#define ECON2_PWRSV 0x20</span>
00173 <span class="preprocessor"></span><span class="preprocessor">#define ECON2_VRPS 0x08</span>
00174 <span class="preprocessor"></span><span class="comment">// ENC28J60 ECON1 Register Bit Definitions</span>
00175 <span class="preprocessor">#define ECON1_TXRST 0x80</span>
00176 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_RXRST 0x40</span>
00177 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_DMAST 0x20</span>
00178 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_CSUMEN 0x10</span>
00179 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_TXRTS 0x08</span>
00180 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_RXEN 0x04</span>
00181 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_BSEL1 0x02</span>
00182 <span class="preprocessor"></span><span class="preprocessor">#define ECON1_BSEL0 0x01</span>
00183 <span class="preprocessor"></span><span class="comment">// ENC28J60 MACON1 Register Bit Definitions</span>
00184 <span class="preprocessor">#define MACON1_LOOPBK 0x10</span>
00185 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_TXPAUS 0x08</span>
00186 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_RXPAUS 0x04</span>
00187 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_PASSALL 0x02</span>
00188 <span class="preprocessor"></span><span class="preprocessor">#define MACON1_MARXEN 0x01</span>
00189 <span class="preprocessor"></span><span class="comment">// ENC28J60 MACON2 Register Bit Definitions</span>
00190 <span class="preprocessor">#define MACON2_MARST 0x80</span>
00191 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_RNDRST 0x40</span>
00192 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_MARXRST 0x08</span>
00193 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_RFUNRST 0x04</span>
00194 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_MATXRST 0x02</span>
00195 <span class="preprocessor"></span><span class="preprocessor">#define MACON2_TFUNRST 0x01</span>
00196 <span class="preprocessor"></span><span class="comment">// ENC28J60 MACON3 Register Bit Definitions</span>
00197 <span class="preprocessor">#define MACON3_PADCFG2 0x80</span>
00198 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_PADCFG1 0x40</span>
00199 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_PADCFG0 0x20</span>
00200 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_TXCRCEN 0x10</span>
00201 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_PHDRLEN 0x08</span>
00202 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_HFRMLEN 0x04</span>
00203 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_FRMLNEN 0x02</span>
00204 <span class="preprocessor"></span><span class="preprocessor">#define MACON3_FULDPX 0x01</span>
00205 <span class="preprocessor"></span><span class="comment">// ENC28J60 MICMD Register Bit Definitions</span>
00206 <span class="preprocessor">#define MICMD_MIISCAN 0x02</span>
00207 <span class="preprocessor"></span><span class="preprocessor">#define MICMD_MIIRD 0x01</span>
00208 <span class="preprocessor"></span><span class="comment">// ENC28J60 MISTAT Register Bit Definitions</span>
00209 <span class="preprocessor">#define MISTAT_NVALID 0x04</span>
00210 <span class="preprocessor"></span><span class="preprocessor">#define MISTAT_SCAN 0x02</span>
00211 <span class="preprocessor"></span><span class="preprocessor">#define MISTAT_BUSY 0x01</span>
00212 <span class="preprocessor"></span><span class="comment">// ENC28J60 PHY PHCON1 Register Bit Definitions</span>
00213 <span class="preprocessor">#define PHCON1_PRST 0x8000</span>
00214 <span class="preprocessor"></span><span class="preprocessor">#define PHCON1_PLOOPBK 0x4000</span>
00215 <span class="preprocessor"></span><span class="preprocessor">#define PHCON1_PPWRSV 0x0800</span>
00216 <span class="preprocessor"></span><span class="preprocessor">#define PHCON1_PDPXMD 0x0100</span>
00217 <span class="preprocessor"></span><span class="comment">// ENC28J60 PHY PHSTAT1 Register Bit Definitions</span>
00218 <span class="preprocessor">#define PHSTAT1_PFDPX 0x1000</span>
00219 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1_PHDPX 0x0800</span>
00220 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1_LLSTAT 0x0004</span>
00221 <span class="preprocessor"></span><span class="preprocessor">#define PHSTAT1_JBSTAT 0x0002</span>
00222 <span class="preprocessor"></span><span class="comment">// ENC28J60 PHY PHCON2 Register Bit Definitions</span>
00223 <span class="preprocessor">#define PHCON2_FRCLINK 0x4000</span>
00224 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2_TXDIS 0x2000</span>
00225 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2_JABBER 0x0400</span>
00226 <span class="preprocessor"></span><span class="preprocessor">#define PHCON2_HDLDIS 0x0100</span>
00227 <span class="preprocessor"></span>
00228 <span class="comment">// ENC28J60 Packet Control Byte Bit Definitions</span>
00229 <span class="preprocessor">#define PKTCTRL_PHUGEEN 0x08</span>
00230 <span class="preprocessor"></span><span class="preprocessor">#define PKTCTRL_PPADEN 0x04</span>
00231 <span class="preprocessor"></span><span class="preprocessor">#define PKTCTRL_PCRCEN 0x02</span>
00232 <span class="preprocessor"></span><span class="preprocessor">#define PKTCTRL_POVERRIDE 0x01</span>
00233 <span class="preprocessor"></span>
00234 <span class="comment">// SPI operation codes</span>
00235 <span class="preprocessor">#define ENC28J60_READ_CTRL_REG 0x00</span>
00236 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_READ_BUF_MEM 0x3A</span>
00237 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_WRITE_CTRL_REG 0x40</span>
00238 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_WRITE_BUF_MEM 0x7A</span>
00239 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_BIT_FIELD_SET 0x80</span>
00240 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_BIT_FIELD_CLR 0xA0</span>
00241 <span class="preprocessor"></span><span class="preprocessor">#define ENC28J60_SOFT_RESET 0xFF</span>
00242 <span class="preprocessor"></span>
00243
00244 <span class="comment">// buffer boundaries applied to internal 8K ram</span>
00245 <span class="comment">// entire available packet buffer space is allocated</span>
00246 <span class="preprocessor">#define TXSTART_INIT 0x0000 // start TX buffer at 0</span>
00247 <span class="preprocessor"></span><span class="preprocessor">#define RXSTART_INIT 0x0600 // give TX buffer space for one full ethernet frame (~1500 bytes)</span>
00248 <span class="preprocessor"></span><span class="preprocessor">#define RXSTOP_INIT 0x1FFF // receive buffer gets the rest</span>
00249 <span class="preprocessor"></span>
00250 <span class="preprocessor">#define MAX_FRAMELEN 1518 // maximum ethernet frame length</span>
00251 <span class="preprocessor"></span>
00252 <span class="comment">// Ethernet constants</span>
00253 <span class="preprocessor">#define ETHERNET_MIN_PACKET_LENGTH 0x3C</span>
00254 <span class="preprocessor"></span><span class="comment">//#define ETHERNET_HEADER_LENGTH 0x0E</span>
00255
00256 <span class="comment">// functions</span>
00257 <span class="preprocessor">#include "<a class="code" href="nic_8h.html">nic.h</a>"</span>
00258
00259 <span class="comment">// setup ports for I/O</span>
00260 <span class="comment">//void ax88796SetupPorts(void);</span>
00261 <span class="comment"></span>
00262 <span class="comment">//! do a ENC28J60 read operation</span>
00263 <span class="comment"></span>u08 <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(u08 <a class="code" href="structnetBootpHeader.html#o0">op</a>, u08 address);<span class="comment"></span>
00264 <span class="comment">//! do a ENC28J60 write operation</span>
00265 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(u08 <a class="code" href="structnetBootpHeader.html#o0">op</a>, u08 address, u08 data);<span class="comment"></span>
00266 <span class="comment">//! read the packet buffer memory</span>
00267 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga2">enc28j60ReadBuffer</a>(u16 len, u08* data);<span class="comment"></span>
00268 <span class="comment">//! write the packet buffer memory</span>
00269 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga3">enc28j60WriteBuffer</a>(u16 len, u08* data);<span class="comment"></span>
00270 <span class="comment">//! set the register bank for register at address</span>
00271 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(u08 address);<span class="comment"></span>
00272 <span class="comment">//! read ax88796 register</span>
00273 <span class="comment"></span>u08 <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(u08 address);<span class="comment"></span>
00274 <span class="comment">//! write ax88796 register</span>
00275 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(u08 address, u08 data);<span class="comment"></span>
00276 <span class="comment">//! read a PHY register</span>
00277 <span class="comment"></span>u16 <a class="code" href="group__enc28j60.html#ga7">enc28j60PhyRead</a>(u08 address);<span class="comment"></span>
00278 <span class="comment">//! write a PHY register</span>
00279 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(u08 address, u16 data);
00280 <span class="comment"></span>
00281 <span class="comment">//! initialize the ethernet interface for transmit/receive</span>
00282 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga9">enc28j60Init</a>(<span class="keywordtype">void</span>);
00283 <span class="comment"></span>
00284 <span class="comment">//! Packet transmit function.</span>
00285 <span class="comment">/// Sends a packet on the network. It is assumed that the packet is headed by a valid ethernet header.</span>
00286 <span class="comment">/// \param len Length of packet in bytes.</span>
00287 <span class="comment">/// \param packet Pointer to packet data.</span>
00288 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga10">enc28j60PacketSend</a>(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> len, <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span>* packet);
00289 <span class="comment"></span>
00290 <span class="comment">//! Packet receive function.</span>
00291 <span class="comment">/// Gets a packet from the network receive buffer, if one is available.</span>
00292 <span class="comment">/// The packet will by headed by an ethernet header.</span>
00293 <span class="comment">/// \param maxlen The maximum acceptable length of a retrieved packet.</span>
00294 <span class="comment">/// \param packet Pointer where packet data should be stored.</span>
00295 <span class="comment">/// \return Packet length in bytes if a packet was retrieved, zero otherwise.</span>
00296 <span class="comment"></span><span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> <a class="code" href="group__enc28j60.html#ga11">enc28j60PacketReceive</a>(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> maxlen, <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span>* packet);
00297 <span class="comment"></span>
00298 <span class="comment">//! execute procedure for recovering from a receive overflow</span>
00299 <span class="comment">/// this should be done when the receive memory fills up with packets</span>
00300 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga12">enc28j60ReceiveOverflowRecover</a>(<span class="keywordtype">void</span>);
00301 <span class="comment"></span>
00302 <span class="comment">//! formatted print of important ENC28J60 registers</span>
00303 <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga13">enc28j60RegDump</a>(<span class="keywordtype">void</span>);
00304
00305 <span class="preprocessor">#endif</span>
00306 <span class="preprocessor"></span><span class="comment">//@}</span>
</span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Sun Oct 29 03:41:07 2006 for Procyon AVRlib by
<a href="http://www.doxygen.org/index.html">
<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.2 </small></address>
</body>
</html>
|
{FILE END}
{FOOTER START}
Powered by WebSVN v2.8.3