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\chap Conclusions

A special design of the scalable data-acquisition system was proposed. This system has unique parameters compared to the state of the art radioastronomy signal processing hardware. The outcome of this diploma project offers the 16bit resolution and such a dynamical range which is not common with others. The conducted experiments demonstrated the system functionality in the instance of the most basic interferometric station. Additional validation of reached parameters would be necessary, though. The fully functional trial version of the fast multi-channel data acquisition part of the radioastronomy receiver was designed and tested in the reported diploma project.

A substantial design and testing experience has been gathered, which will be utilized in the final design aiming at becoming the part of MLAB Advanced Radio Astronomy System~\cite[mlab-aras]. However, additional experimenting is needed.

All requirements demanded by the thesis specification have been reached and/or exceeded. The required minimal sampling frequency of 1 MHz has been exceeded five times at least. The requested dynamical range specified by 12 bits have been exceeded at least by 8 dB in the decibel scale. As a by-pass product of digitization unit design, the software defined GPS disciplined oscillator device has been developed. This device is currently in use in several radio meteor detection stations in the Czech Republic. On other hand the proposed design is not still perfect and some minor imperfections should be corrected in future work.

The work also attracted the interest of the research team at the Czech Technical University in Prague, Faculty of Electrical Engineering in the project MUMOIRE, which has been solved in collaboration and for the US Missile Defense Agency. MUMOIRE team seeks space debris detection/observation methods, which fuse observations from the optical telescope and the radar. The multi-channel data acquisition part of the receiver should provide better radar observations in which French radar GRAVES serves as the energy source.

\sec Possible hardware improvements

The PCB design of the used modules might need a more precise high-speed optimization of differential pairs. Improvement in the high-speed routing allows a possible use of the fastest ADC from the Linear Technology devices family. The use of the faster ADCs could even improve a range of possible applications.

Minor ADC module imperfections, such as the unnecessary separation of FRAME and DCO signal to two connectors, should be mitigated. These two signals should be merged together to one SATA connector. With this modification, we will be able to remove one redundant SATA cable between the analog to digital converter device and the computational unit section.

\sec Possible software improvements

In the future versions of the system hardware, the Xillybus IP core and driver interface should be swapped with an open-source alternative of PCIe interfacing module or PCIe might be completely avoided. In ADC configuration FPGA module, the SPI configuration data registers read back should be implemented.

\nonum \chap Glossary

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