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%% OPmac - REF file
\Xpage{-1}
\Xpage{-2}
\Xpage{-3}
\Xpage{-4}
\Xpage{-5}
\Xpage{-6}
\Xpage{1}
\Xchap{1}{Introduction }{1}
\Xsec{1.1}{Current radioastronomy problems }{1}
\Xfnote
\Xpage{2}
\Xsec{1.2}{Modern Radio astronomy receiver }{2}
\Xfnote
\Xsecc{1.2.1}{Observation types }{2}
\Xpage{3}
\Xsec{1.3}{Required receiver parameters }{3}
\Xsecc{1.3.1}{Sensitivity and noise number }{3}
\Xsecc{1.3.2}{Dynamic range }{3}
\Xtab{ADC-dynamic-range}{1.1}{Dynamic range versus bit depth}
\Xlabel{ADC-dynamic-range}{1.1}
\Xsecc{1.3.3}{Bandwidth }{3}
\Xpage{4}
\Xchap{2}{Trial design }{4}
\Xsec{2.1}{Required parameters }{4}
\Xsec{2.2}{Sampling frequency }{4}
\Xsec{2.3}{System scalability }{4}
\Xpage{5}
\Xsecc{2.3.1}{Differential signalling }{5}
\Xsecc{2.3.2}{Phase matching }{5}
\Xsec{2.4}{System description }{5}
\Xsecc{2.4.1}{Frequency synthesis }{5}
\Xfnote
\Xpage{6}
\Xsecc{2.4.2}{Signal cable connectors }{6}
\Xsecc{2.4.3}{Signal integrity requirements }{6}
\Xsecc{2.4.4}{ADC modules design }{6}
\Xpage{7}
\Xfig{img-miniSAS-cable}{2.1}{Used miniSAS cable}
\Xlabel{img-miniSAS-cable}{2.1}
\Xsecc{2.4.5}{ADC selection }{7}
\Xpage{8}
\Xtab{ADC-types}{2.1}{Available ADC types}
\Xlabel{ADC-types}{2.1}
\Xsecc{2.4.6}{ADC modules interface }{8}
\Xsecc{2.4.7}{Output data format }{8}
\Xsec{2.5}{Achieved parameters }{8}
\Xpage{9}
\Xfig{VITA57-regions}{2.3}{VITA57 board geometry}
\Xlabel{VITA57-regions}{2.3}
\Xsecc{2.5.1}{Data reading and recording }{9}
\Xpage{10}
\Xpage{11}
\Xsecc{2.5.2}{ADC module parameters }{11}
\Xpage{12}
\Xpage{13}
\Xchap{3}{Example of usage }{13}
\Xsec{3.1}{Basic interferometer station }{13}
\Xfig{meteor-reflection}{3.1}{Meteor reflection}
\Xlabel{meteor-reflection}{3.1}
\Xfig{phase-phase-difference}{3.2}{Phase difference}
\Xlabel{phase-phase-difference}{3.2}
\Xpage{14}
\Xfig{block-schematic}{3.3}{Receiver block schematic}
\Xlabel{block-schematic}{3.3}
\Xpage{15}
\Xchap{4}{Proposed final system }{15}
\Xsec{4.1}{Custom design of FPGA board }{15}
\Xsec{4.2}{Parralella board computer }{15}
\Xsec{4.3}{GPU based computational system }{15}
\Xpage{16}
\Xfig{img-NVIDIA-K1}{4.1}{NVIDIA Jetson TK1 Development Kit}
\Xlabel{img-NVIDIA-K1}{4.1}
\Xpage{17}
\Xchap{5}{Conclusion }{17}
\Xsec{5.1}{Possible future improvements }{17}
\Xpage{19}
\Xchap{A}{Circuit diagram of ADCdual01A module }{19}
\Xpage{20}
\Xchap{B}{Circuit diagram of FMC2DIFF module }{20}
\Xpage{21}
\Xpage{22}
\Xpage{23}
\Xpage{24}