Rev 1844 – ?author? – ?age? (?date?)
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(root)
/
Modules
/
Clock
/
CLKGEN01B/
@ 3582
Rev 1844
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Log message
Diff
1711
5085 d 18 h
kaklik
/Modules/Clock/CLKGEN01B/
uprava zemeni a rozlozeni soucastek
Diff
1691
5111 d 22 h
kaklik
/
Fifmware zeditovan tak, aby nepotreboval bootloader.
Diff
1668
5124 d 19 h
kaklik
/Modules/
nove moduly
Diff
1666
5130 d 7 h
kaklik
/Modules/
Zalozeni noveho typu modulu pro Time to Digital conversion
Diff
1661
5139 d 20 h
kaklik
/Modules/Clock/CLKGEN01A/SW/DG8SAQ synthesiser_Emulator/
do MLABu naportovan program pro ovladani kmitoctove syntezy z pocitace.
Diff
1572
5202 d 10 h
kaklik
/
poznamky problemu
Diff
1555
5230 d 18 h
kaklik
/Modules/Clock/
pokus s ladenim delky spoju
Diff
1548
5241 d 6 h
kaklik
/Modules/Clock/
aktualizace popisu modulů.
Diff
1547
5241 d 6 h
kaklik
/Modules/Clock/CLKGEN01A/
Fotky LO.
Diff
1546
5244 d 3 h
kaklik
/Modules/Clock/CLKGEN01A/
seznam chyb.
Diff
1545
5244 d 4 h
kaklik
/Modules/Clock/CLKGEN01A/
potisk
Diff
1544
5245 d 5 h
kaklik
/
Diff
1543
5245 d 6 h
kaklik
/Modules/Clock/CLKGEN01A/
vymena CAM vystupu
Diff
1542
5245 d 7 h
kaklik
/Modules/Clock/CLKGEN01A/
generovani technologickych dat.
Diff
1541
5245 d 19 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
Diff
1540
5245 d 20 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
Diff
1539
5245 d 20 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
Diff
1531
5262 d 19 h
kaklik
/Modules/Clock/CLKGEN01A/
pridani chybejicich terminacnich odporu..
Diff
1530
5263 d 3 h
kaklik
/Modules/Clock/CLKGEN01A/
Temer konecna verze PCB pro Si570. Respektive Si5XX
Diff
1529
5263 d 4 h
kaklik
/Modules/Clock/CLKGEN01A/
Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru.
Diff