Rev Age Author Path Log message Diff Changes
4962 2044 d 19 h kaklik /Designs/ Renaming HAM Constructions directory to allow import on github. Diff
/Designs/HAM_Constructions
/Designs/HAM Constructions
3641 3853 d 23 h kaklik /Designs/HAM Constructions/SDRX02B/HDL/ Pridani HDL zdrojovych kodu. Diff
/Designs/HAM Constructions/SDRX02B/HDL
/Designs/HAM Constructions/SDRX02B/HDL/README.txt
/Designs/HAM Constructions/SDRX02B/HDL/modules
/Designs/HAM Constructions/SDRX02B/HDL/modules/comm
/Designs/HAM Constructions/SDRX02B/HDL/modules/comm/spi_master_transmit.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/clk_125MHz_to_6MHz.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512_dualclk_fwft.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512_walmostfull.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/fifo_related
/Designs/HAM Constructions/SDRX02B/HDL/modules/fifo_related/fifo_to_enable.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/information
/Designs/HAM Constructions/SDRX02B/HDL/modules/information/information_block.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/clock_divider.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/up_counter.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/up_counter_stdlv.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/xilly
/Designs/HAM Constructions/SDRX02B/HDL/modules/xilly/xilly_userlogiccmp_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src
/Designs/HAM Constructions/SDRX02B/HDL/project_src/bitslip_compensation.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/glue_data.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/information_data.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/iserdes_clock_generator.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/kakona_package.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/lo_divider_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/multiplexer_from_fifos.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/myserdes_ddr.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/myserdes_ddr_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/processing_block.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/saw_generator_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/spi_transmitter_wrapper2.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/swap_endianness.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/userlogiccmp_template.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/xilly
/Designs/HAM Constructions/SDRX02B/HDL/project_src/xilly/xilly_toplevel.userlogiccmp_kakona.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/xillybus_ml605_kakona.ucf