Last modification
Rev 0 – miho – 5035 d 5 h
Log message
Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A
Path Blame Diff Log
/Modules/CPLD_FPGA/S3AN01A/ Log
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/ Log
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/T1_AMA.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_AMA.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_REAL.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/ Log
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/Drill.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O1.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O2.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V1.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V2.pdf Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/ Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/BOARD.PHO Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.DRL Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.rep Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M1.PHO Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M2.PHO Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/P2.PHO Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/T1.PHO Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V1.PHO Log
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V2.PHO Log
/Modules/CPLD_FPGA/S3AN01A/PCB/ Log
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb Log
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt Log
/Modules/CPLD_FPGA/S3AN01A/SCH/ Log
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC Log
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN Log
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls Log
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf Log