Last modification
Rev 0 – kaklik – 3983 d 12 h
Log message
prvni schema a plosny spoj modulu delicky.
Path Blame Diff Log
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb Log
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc Log
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN Log
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj Log